queue size: 0 starting:Qsys "Qsys" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 20 modules, 83 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 16 modules, 61 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform 33 modules, 128 connections]]> Transform: IDPadTransform Transform: DomainTransform Transform merlin_domain_transform not run on matched interfaces nios2_gen2.data_master and nios2_gen2_data_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces nios2_gen2.instruction_master and nios2_gen2_instruction_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave Transform merlin_domain_transform not run on matched interfaces i2c_opencores_mipi_avalon_slave_0_translator.avalon_anti_slave_0 and i2c_opencores_mipi.avalon_slave_0 Transform merlin_domain_transform not run on matched interfaces i2c_opencores_camera_avalon_slave_0_translator.avalon_anti_slave_0 and i2c_opencores_camera.avalon_slave_0 Transform merlin_domain_transform not run on matched interfaces sysid_qsys_control_slave_translator.avalon_anti_slave_0 and sysid_qsys.control_slave Transform merlin_domain_transform not run on matched interfaces nios2_gen2_debug_mem_slave_translator.avalon_anti_slave_0 and nios2_gen2.debug_mem_slave Transform merlin_domain_transform not run on matched interfaces TERASIC_AUTO_FOCUS_0_mm_ctrl_translator.avalon_anti_slave_0 and TERASIC_AUTO_FOCUS_0.mm_ctrl Transform merlin_domain_transform not run on matched interfaces altpll_0_pll_slave_translator.avalon_anti_slave_0 and altpll_0.pll_slave Transform merlin_domain_transform not run on matched interfaces onchip_memory2_0_s1_translator.avalon_anti_slave_0 and onchip_memory2_0.s1 Transform merlin_domain_transform not run on matched interfaces timer_s1_translator.avalon_anti_slave_0 and timer.s1 Transform merlin_domain_transform not run on matched interfaces led_s1_translator.avalon_anti_slave_0 and led.s1 Transform merlin_domain_transform not run on matched interfaces sw_s1_translator.avalon_anti_slave_0 and sw.s1 Transform merlin_domain_transform not run on matched interfaces key_s1_translator.avalon_anti_slave_0 and key.s1 Transform merlin_domain_transform not run on matched interfaces mipi_reset_n_s1_translator.avalon_anti_slave_0 and mipi_reset_n.s1 Transform merlin_domain_transform not run on matched interfaces mipi_pwdn_n_s1_translator.avalon_anti_slave_0 and mipi_pwdn_n.s1 Transform merlin_domain_transform not run on matched interfaces EEE_IMGPROC_0_s1_translator.avalon_anti_slave_0 and EEE_IMGPROC_0.s1 68 modules, 359 connections]]> Transform: RouterTransform 85 modules, 426 connections]]> Transform: TrafficLimiterTransform 87 modules, 436 connections]]> Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform 120 modules, 520 connections]]> Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0 Inserting clock-crossing logic between cmd_demux.src14 and cmd_mux_014.sink0 Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5 Inserting clock-crossing logic between rsp_demux_014.src0 and rsp_mux.sink14 124 modules, 548 connections]]> Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform 124 modules, 550 connections]]> Transform: InsertClockAndResetBridgesTransform 129 modules, 682 connections]]> Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 21 modules, 90 connections]]> Transform: InitialInterconnectTransform 5 modules, 8 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform 8 modules, 20 connections]]> Transform: IDPadTransform Transform: DomainTransform Transform merlin_domain_transform not run on matched interfaces alt_vip_vfb_0.read_master and alt_vip_vfb_0_read_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces alt_vip_vfb_0.write_master and alt_vip_vfb_0_write_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces sdram_s1_translator.avalon_anti_slave_0 and sdram.s1 14 modules, 55 connections]]> Transform: RouterTransform 17 modules, 67 connections]]> Transform: TrafficLimiterTransform Transform: BurstTransform 18 modules, 71 connections]]> Transform: TreeTransform Transform: NetworkToSwitchTransform 23 modules, 84 connections]]> Transform: WidthTransform 25 modules, 92 connections]]> Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform 27 modules, 116 connections]]> Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 22 modules, 94 connections]]> 22 modules, 94 connections]]> Transform: InterruptMapperTransform 23 modules, 98 connections]]> Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation 27 modules, 97 connections]]> Qsys" reuses EEE_IMGPROC "submodules/EEE_IMGPROC"]]> Qsys" reuses TERASIC_AUTO_FOCUS "submodules/TERASIC_AUTO_FOCUS"]]> Qsys" reuses TERASIC_CAMERA "submodules/TERASIC_CAMERA"]]> Qsys" reuses alt_vip_itc "submodules/alt_vipitc131_IS2Vid"]]> Qsys" reuses alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0"]]> Qsys" reuses altpll "submodules/Qsys_altpll_0"]]> Qsys" reuses i2c_opencores "submodules/i2c_opencores"]]> Qsys" reuses i2c_opencores "submodules/i2c_opencores"]]> Qsys" reuses altera_avalon_jtag_uart "submodules/Qsys_jtag_uart"]]> Qsys" reuses altera_avalon_pio "submodules/Qsys_key"]]> Qsys" reuses altera_avalon_pio "submodules/Qsys_led"]]> Qsys" reuses altera_avalon_pio "submodules/Qsys_mipi_pwdn_n"]]> Qsys" reuses altera_avalon_pio "submodules/Qsys_mipi_pwdn_n"]]> Qsys" reuses altera_nios2_gen2 "submodules/Qsys_nios2_gen2"]]> Qsys" reuses altera_avalon_onchip_memory2 "submodules/Qsys_onchip_memory2_0"]]> Qsys" reuses altera_avalon_new_sdram_controller "submodules/Qsys_sdram"]]> Qsys" reuses altera_avalon_pio "submodules/Qsys_sw"]]> Qsys" reuses altera_avalon_sysid_qsys "submodules/Qsys_sysid_qsys"]]> Qsys" reuses altera_avalon_timer "submodules/Qsys_timer"]]> Qsys" reuses altera_mm_interconnect "submodules/Qsys_mm_interconnect_0"]]> Qsys" reuses altera_mm_interconnect "submodules/Qsys_mm_interconnect_1"]]> Qsys" reuses altera_irq_mapper "submodules/Qsys_irq_mapper"]]> Qsys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> Qsys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> Qsys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> queue size: 24 starting:EEE_IMGPROC "submodules/EEE_IMGPROC" Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0"]]> queue size: 23 starting:TERASIC_AUTO_FOCUS "submodules/TERASIC_AUTO_FOCUS" Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"]]> queue size: 22 starting:TERASIC_CAMERA "submodules/TERASIC_CAMERA" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0002_sopcqmap/not_a_project_setup.tcl Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0002_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on Command took 0.625s Command took 0.719s set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0005_sopcqmap/not_a_project_setup.tcl Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\ip\TERASIC_CAMERA\TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0005_sopcqmap/ --set=HDL_INTERFACE_INSTANCE_NAME=inst --set=HDL_INTERFACE_INSTANCE_ENTITY=TERASIC_CAMERA "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=VIDEO_W=D\"640\";VIDEO_H=D\"480\";" --ini=disable_check_quartus_compatibility_qsys_only=on Command took 0.614s Command took 0.704s Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"]]> queue size: 21 starting:alt_vip_itc "submodules/alt_vipitc131_IS2Vid" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0006_sopcqmap/not_a_project_setup.tcl Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0006_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on Command took 0.616s Command took 0.718s set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0007_sopcqmap/not_a_project_setup.tcl Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:\intelfpga_lite\16.1\ip\altera\clocked_video_output\src_hdl\alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0007_sopcqmap/ --set=HDL_INTERFACE_INSTANCE_NAME=inst --set=HDL_INTERFACE_INSTANCE_ENTITY=alt_vipitc131_IS2Vid "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=NUMBER_OF_COLOUR_PLANES=D\"3\";COLOUR_PLANES_ARE_IN_PARALLEL=D\"1\";BPS=D\"8\";INTERLACED=D\"0\";H_ACTIVE_PIXELS=D\"640\";V_ACTIVE_LINES=D\"480\";ACCEPT_COLOURS_IN_SEQ=D\"0\";FIFO_DEPTH=D\"640\";CLOCKS_ARE_SAME=D\"0\";USE_CONTROL=D\"0\";NO_OF_MODES=D\"1\";THRESHOLD=D\"639\";STD_WIDTH=D\"1\";GENERATE_SYNC=D\"0\";USE_EMBEDDED_SYNCS=D\"0\";AP_LINE=D\"0\";V_BLANK=D\"0\";H_BLANK=D\"0\";H_SYNC_LENGTH=D\"96\";H_FRONT_PORCH=D\"16\";H_BACK_PORCH=D\"48\";V_SYNC_LENGTH=D\"2\";V_FRONT_PORCH=D\"10\";V_BACK_PORCH=D\"33\";F_RISING_EDGE=D\"0\";F_FALLING_EDGE=D\"0\";FIELD0_V_RISING_EDGE=D\"0\";FIELD0_V_BLANK=D\"0\";FIELD0_V_SYNC_LENGTH=D\"0\";FIELD0_V_FRONT_PORCH=D\"0\";FIELD0_V_BACK_PORCH=D\"0\";ANC_LINE=D\"0\";FIELD0_ANC_LINE=D\"0\";" --ini=disable_check_quartus_compatibility_qsys_only=on Command took 0.588s Command took 0.750s Qsys" instantiated alt_vip_itc "alt_vip_itc_0"]]> queue size: 20 starting:alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0" alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_avalon_st_input "submodules/alt_cusp161_avalon_st_input"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_avalon_st_output "submodules/alt_cusp161_avalon_st_output"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_pulling_width_adapter "submodules/alt_cusp161_pulling_width_adapter"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_pushing_width_adapter "submodules/alt_cusp161_pushing_width_adapter"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp161_pc"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp161_pc"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> dut" reuses alt_cusp_testbench_clock "submodules/alt_cusp161_clock_reset"]]> dut" reuses alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0"]]> Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"]]> queue size: 343 starting:alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2" alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"]]> queue size: 341 starting:alt_au "submodules/alt_cusp161_au" alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"]]> queue size: 332 starting:alt_reg "submodules/alt_cusp161_reg" alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 331 starting:alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16" alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"]]> queue size: 307 starting:alt_avalon_st_input "submodules/alt_cusp161_avalon_st_input" alt_vip_vfb_0" instantiated alt_avalon_st_input "din"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 302 starting:alt_avalon_st_output "submodules/alt_cusp161_avalon_st_output" alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 298 starting:alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo" alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 296 starting:alt_cusp_pulling_width_adapter "submodules/alt_cusp161_pulling_width_adapter" alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 290 starting:alt_cusp_pushing_width_adapter "submodules/alt_cusp161_pushing_width_adapter" alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 256 starting:alt_pc "submodules/alt_cusp161_pc" alt_vip_vfb_0" instantiated alt_pc "pc0"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 196 starting:alt_cmp "submodules/alt_cusp161_cmp" alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 146 starting:alt_cusp_testbench_clock "submodules/alt_cusp161_clock_reset" alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 218 starting:altpll "submodules/Qsys_altpll_0" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0008_sopcgen/Qsys_altpll_0.v --source=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0008_sopcgen/Qsys_altpll_0.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0009_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on Command took 0.841s Qsys" instantiated altpll "altpll_0"]]> queue size: 217 starting:i2c_opencores "submodules/i2c_opencores" Qsys" instantiated i2c_opencores "i2c_opencores_camera"]]> queue size: 215 starting:altera_avalon_jtag_uart "submodules/Qsys_jtag_uart" Starting RTL generation for module 'Qsys_jtag_uart' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_jtag_uart' Qsys" instantiated altera_avalon_jtag_uart "jtag_uart"]]> queue size: 214 starting:altera_avalon_pio "submodules/Qsys_key" Starting RTL generation for module 'Qsys_key' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_key' Qsys" instantiated altera_avalon_pio "key"]]> queue size: 213 starting:altera_avalon_pio "submodules/Qsys_led" Starting RTL generation for module 'Qsys_led' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_led' Qsys" instantiated altera_avalon_pio "led"]]> queue size: 212 starting:altera_avalon_pio "submodules/Qsys_mipi_pwdn_n" Starting RTL generation for module 'Qsys_mipi_pwdn_n' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_mipi_pwdn_n' Qsys" instantiated altera_avalon_pio "mipi_pwdn_n"]]> queue size: 210 starting:altera_nios2_gen2 "submodules/Qsys_nios2_gen2" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation nios2_gen2" reuses altera_nios2_gen2_unit "submodules/Qsys_nios2_gen2_cpu"]]> Qsys" instantiated altera_nios2_gen2 "nios2_gen2"]]> queue size: 144 starting:altera_nios2_gen2_unit "submodules/Qsys_nios2_gen2_cpu" Starting RTL generation for module 'Qsys_nios2_gen2_cpu' Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ] # 2021.05.27 17:51:00 (*) Starting Nios II generation # 2021.05.27 17:51:00 (*) Checking for plaintext license. # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty # 2021.05.27 17:51:01 (*) Plaintext license not found. # 2021.05.27 17:51:01 (*) Checking for encrypted license (non-evaluation). # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty # 2021.05.27 17:51:01 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF) # 2021.05.27 17:51:01 (*) Elaborating CPU configuration settings # 2021.05.27 17:51:01 (*) Creating all objects for CPU # 2021.05.27 17:51:01 (*) Testbench # 2021.05.27 17:51:02 (*) Instruction decoding # 2021.05.27 17:51:02 (*) Instruction fields # 2021.05.27 17:51:02 (*) Instruction decodes # 2021.05.27 17:51:02 (*) Signals for RTL simulation waveforms # 2021.05.27 17:51:02 (*) Instruction controls # 2021.05.27 17:51:02 (*) Pipeline frontend # 2021.05.27 17:51:02 (*) Pipeline backend # 2021.05.27 17:51:05 (*) Generating RTL from CPU objects # 2021.05.27 17:51:06 (*) Creating encrypted RTL # 2021.05.27 17:51:07 (*) Done Nios II generation Done RTL generation for module 'Qsys_nios2_gen2_cpu' nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 210 starting:altera_avalon_onchip_memory2 "submodules/Qsys_onchip_memory2_0" Starting RTL generation for module 'Qsys_onchip_memory2_0' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_onchip_memory2_0' Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"]]> queue size: 209 starting:altera_avalon_new_sdram_controller "submodules/Qsys_sdram" Starting RTL generation for module 'Qsys_sdram' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_sdram' Qsys" instantiated altera_avalon_new_sdram_controller "sdram"]]> queue size: 208 starting:altera_avalon_pio "submodules/Qsys_sw" Starting RTL generation for module 'Qsys_sw' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_sw' Qsys" instantiated altera_avalon_pio "sw"]]> queue size: 207 starting:altera_avalon_sysid_qsys "submodules/Qsys_sysid_qsys" Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys"]]> queue size: 206 starting:altera_avalon_timer "submodules/Qsys_timer" Starting RTL generation for module 'Qsys_timer' Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_timer' Qsys" instantiated altera_avalon_timer "timer"]]> queue size: 205 starting:altera_mm_interconnect "submodules/Qsys_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 113 modules, 386 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.029s/0.039s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.012s/0.013s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.013s/0.014s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.007s Timing: COM:3/0.012s/0.012s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.007s Timing: COM:3/0.017s/0.027s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.007s Timing: COM:3/0.013s/0.016s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.006s Timing: COM:3/0.012s/0.014s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.007s Timing: COM:3/0.012s/0.013s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.016s/0.024s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.008s Timing: COM:3/0.012s/0.013s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.006s Timing: COM:3/0.011s/0.012s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.007s Timing: COM:3/0.011s/0.012s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.015s/0.022s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.011s/0.012s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.006s Timing: COM:3/0.012s/0.015s 128 modules, 431 connections]]> Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_001"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> mm_interconnect_0" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux_001"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux_001"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> Qsys" instantiated altera_mm_interconnect "mm_interconnect_0"]]> queue size: 143 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"]]> queue size: 141 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 126 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"]]> queue size: 124 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 123 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 92 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 91 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> queue size: 90 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> queue size: 86 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006" mm_interconnect_0" instantiated altera_merlin_router "router_006"]]> queue size: 75 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 73 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 72 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux_001" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> queue size: 71 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> queue size: 67 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 56 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 52 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"]]> queue size: 51 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"]]> queue size: 41 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 40 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux_001" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 39 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> queue size: 35 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 1 starting:error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 327 starting:altera_mm_interconnect "submodules/Qsys_mm_interconnect_1" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 22 modules, 64 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 22 modules, 64 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 22 modules, 64 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 22 modules, 64 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.006s Timing: COM:3/0.012s/0.013s 23 modules, 67 connections]]> Transform: ResetAdaptation mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router_002"]]> mm_interconnect_1" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_cmd_mux"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_rsp_demux"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux"]]> mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter"]]> Qsys" instantiated altera_mm_interconnect "mm_interconnect_1"]]> queue size: 143 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"]]> queue size: 141 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 126 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"]]> queue size: 124 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 123 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 13 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router" mm_interconnect_1" instantiated altera_merlin_router "router"]]> queue size: 11 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router_002" mm_interconnect_1" instantiated altera_merlin_router "router_002"]]> queue size: 10 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> queue size: 9 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 7 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_cmd_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 6 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_rsp_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 5 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 3 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 1 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 347 starting:altera_irq_mapper "submodules/Qsys_irq_mapper" Qsys" instantiated altera_irq_mapper "irq_mapper"]]> queue size: 346 starting:altera_reset_controller "submodules/altera_reset_controller" Qsys" instantiated altera_reset_controller "rst_controller"]]> queue size: 24 starting:EEE_IMGPROC "submodules/EEE_IMGPROC" Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0"]]> queue size: 23 starting:TERASIC_AUTO_FOCUS "submodules/TERASIC_AUTO_FOCUS" Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"]]> queue size: 22 starting:TERASIC_CAMERA "submodules/TERASIC_CAMERA" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0002_sopcqmap/not_a_project_setup.tcl Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0002_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on Command took 0.625s Command took 0.719s set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0005_sopcqmap/not_a_project_setup.tcl Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\ip\TERASIC_CAMERA\TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0005_sopcqmap/ --set=HDL_INTERFACE_INSTANCE_NAME=inst --set=HDL_INTERFACE_INSTANCE_ENTITY=TERASIC_CAMERA "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=VIDEO_W=D\"640\";VIDEO_H=D\"480\";" --ini=disable_check_quartus_compatibility_qsys_only=on Command took 0.614s Command took 0.704s Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"]]> queue size: 21 starting:alt_vip_itc "submodules/alt_vipitc131_IS2Vid" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0006_sopcqmap/not_a_project_setup.tcl Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0006_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on Command took 0.616s Command took 0.718s set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0007_sopcqmap/not_a_project_setup.tcl Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:\intelfpga_lite\16.1\ip\altera\clocked_video_output\src_hdl\alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0007_sopcqmap/ --set=HDL_INTERFACE_INSTANCE_NAME=inst --set=HDL_INTERFACE_INSTANCE_ENTITY=alt_vipitc131_IS2Vid "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=NUMBER_OF_COLOUR_PLANES=D\"3\";COLOUR_PLANES_ARE_IN_PARALLEL=D\"1\";BPS=D\"8\";INTERLACED=D\"0\";H_ACTIVE_PIXELS=D\"640\";V_ACTIVE_LINES=D\"480\";ACCEPT_COLOURS_IN_SEQ=D\"0\";FIFO_DEPTH=D\"640\";CLOCKS_ARE_SAME=D\"0\";USE_CONTROL=D\"0\";NO_OF_MODES=D\"1\";THRESHOLD=D\"639\";STD_WIDTH=D\"1\";GENERATE_SYNC=D\"0\";USE_EMBEDDED_SYNCS=D\"0\";AP_LINE=D\"0\";V_BLANK=D\"0\";H_BLANK=D\"0\";H_SYNC_LENGTH=D\"96\";H_FRONT_PORCH=D\"16\";H_BACK_PORCH=D\"48\";V_SYNC_LENGTH=D\"2\";V_FRONT_PORCH=D\"10\";V_BACK_PORCH=D\"33\";F_RISING_EDGE=D\"0\";F_FALLING_EDGE=D\"0\";FIELD0_V_RISING_EDGE=D\"0\";FIELD0_V_BLANK=D\"0\";FIELD0_V_SYNC_LENGTH=D\"0\";FIELD0_V_FRONT_PORCH=D\"0\";FIELD0_V_BACK_PORCH=D\"0\";ANC_LINE=D\"0\";FIELD0_ANC_LINE=D\"0\";" --ini=disable_check_quartus_compatibility_qsys_only=on Command took 0.588s Command took 0.750s Qsys" instantiated alt_vip_itc "alt_vip_itc_0"]]> queue size: 20 starting:alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0" alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_avalon_st_input "submodules/alt_cusp161_avalon_st_input"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_avalon_st_output "submodules/alt_cusp161_avalon_st_output"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_pulling_width_adapter "submodules/alt_cusp161_pulling_width_adapter"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_pushing_width_adapter "submodules/alt_cusp161_pushing_width_adapter"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp161_pc"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp161_pc"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> dut" reuses alt_cusp_testbench_clock "submodules/alt_cusp161_clock_reset"]]> dut" reuses alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0"]]> Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"]]> queue size: 343 starting:alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2" alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"]]> queue size: 341 starting:alt_au "submodules/alt_cusp161_au" alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"]]> queue size: 332 starting:alt_reg "submodules/alt_cusp161_reg" alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 331 starting:alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16" alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"]]> queue size: 307 starting:alt_avalon_st_input "submodules/alt_cusp161_avalon_st_input" alt_vip_vfb_0" instantiated alt_avalon_st_input "din"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 302 starting:alt_avalon_st_output "submodules/alt_cusp161_avalon_st_output" alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 298 starting:alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo" alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 296 starting:alt_cusp_pulling_width_adapter "submodules/alt_cusp161_pulling_width_adapter" alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 290 starting:alt_cusp_pushing_width_adapter "submodules/alt_cusp161_pushing_width_adapter" alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 256 starting:alt_pc "submodules/alt_cusp161_pc" alt_vip_vfb_0" instantiated alt_pc "pc0"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 196 starting:alt_cmp "submodules/alt_cusp161_cmp" alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 146 starting:alt_cusp_testbench_clock "submodules/alt_cusp161_clock_reset" alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 218 starting:altpll "submodules/Qsys_altpll_0" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0008_sopcgen/Qsys_altpll_0.v --source=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0008_sopcgen/Qsys_altpll_0.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0009_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on Command took 0.841s Qsys" instantiated altpll "altpll_0"]]> queue size: 217 starting:i2c_opencores "submodules/i2c_opencores" Qsys" instantiated i2c_opencores "i2c_opencores_camera"]]> queue size: 215 starting:altera_avalon_jtag_uart "submodules/Qsys_jtag_uart" Starting RTL generation for module 'Qsys_jtag_uart' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_jtag_uart' Qsys" instantiated altera_avalon_jtag_uart "jtag_uart"]]> queue size: 214 starting:altera_avalon_pio "submodules/Qsys_key" Starting RTL generation for module 'Qsys_key' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_key' Qsys" instantiated altera_avalon_pio "key"]]> queue size: 213 starting:altera_avalon_pio "submodules/Qsys_led" Starting RTL generation for module 'Qsys_led' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_led' Qsys" instantiated altera_avalon_pio "led"]]> queue size: 212 starting:altera_avalon_pio "submodules/Qsys_mipi_pwdn_n" Starting RTL generation for module 'Qsys_mipi_pwdn_n' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_mipi_pwdn_n' Qsys" instantiated altera_avalon_pio "mipi_pwdn_n"]]> queue size: 210 starting:altera_nios2_gen2 "submodules/Qsys_nios2_gen2" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation nios2_gen2" reuses altera_nios2_gen2_unit "submodules/Qsys_nios2_gen2_cpu"]]> Qsys" instantiated altera_nios2_gen2 "nios2_gen2"]]> queue size: 144 starting:altera_nios2_gen2_unit "submodules/Qsys_nios2_gen2_cpu" Starting RTL generation for module 'Qsys_nios2_gen2_cpu' Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ] # 2021.05.27 17:51:00 (*) Starting Nios II generation # 2021.05.27 17:51:00 (*) Checking for plaintext license. # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty # 2021.05.27 17:51:01 (*) Plaintext license not found. # 2021.05.27 17:51:01 (*) Checking for encrypted license (non-evaluation). # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty # 2021.05.27 17:51:01 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF) # 2021.05.27 17:51:01 (*) Elaborating CPU configuration settings # 2021.05.27 17:51:01 (*) Creating all objects for CPU # 2021.05.27 17:51:01 (*) Testbench # 2021.05.27 17:51:02 (*) Instruction decoding # 2021.05.27 17:51:02 (*) Instruction fields # 2021.05.27 17:51:02 (*) Instruction decodes # 2021.05.27 17:51:02 (*) Signals for RTL simulation waveforms # 2021.05.27 17:51:02 (*) Instruction controls # 2021.05.27 17:51:02 (*) Pipeline frontend # 2021.05.27 17:51:02 (*) Pipeline backend # 2021.05.27 17:51:05 (*) Generating RTL from CPU objects # 2021.05.27 17:51:06 (*) Creating encrypted RTL # 2021.05.27 17:51:07 (*) Done Nios II generation Done RTL generation for module 'Qsys_nios2_gen2_cpu' nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 210 starting:altera_avalon_onchip_memory2 "submodules/Qsys_onchip_memory2_0" Starting RTL generation for module 'Qsys_onchip_memory2_0' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_onchip_memory2_0' Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"]]> queue size: 209 starting:altera_avalon_new_sdram_controller "submodules/Qsys_sdram" Starting RTL generation for module 'Qsys_sdram' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_sdram' Qsys" instantiated altera_avalon_new_sdram_controller "sdram"]]> queue size: 208 starting:altera_avalon_pio "submodules/Qsys_sw" Starting RTL generation for module 'Qsys_sw' Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_sw' Qsys" instantiated altera_avalon_pio "sw"]]> queue size: 207 starting:altera_avalon_sysid_qsys "submodules/Qsys_sysid_qsys" Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys"]]> queue size: 206 starting:altera_avalon_timer "submodules/Qsys_timer" Starting RTL generation for module 'Qsys_timer' Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'Qsys_timer' Qsys" instantiated altera_avalon_timer "timer"]]> queue size: 205 starting:altera_mm_interconnect "submodules/Qsys_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 113 modules, 386 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 113 modules, 386 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.029s/0.039s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.012s/0.013s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.013s/0.014s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.007s Timing: COM:3/0.012s/0.012s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.007s Timing: COM:3/0.017s/0.027s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.007s Timing: COM:3/0.013s/0.016s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.006s Timing: COM:3/0.012s/0.014s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.007s Timing: COM:3/0.012s/0.013s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.016s/0.024s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.008s Timing: COM:3/0.012s/0.013s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.006s Timing: COM:3/0.011s/0.012s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.007s Timing: COM:3/0.011s/0.012s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.015s/0.022s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.007s Timing: COM:3/0.011s/0.012s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.006s Timing: COM:3/0.012s/0.015s 128 modules, 431 connections]]> Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_001"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> mm_interconnect_0" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> mm_interconnect_0" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux_001"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux_001"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> Qsys" instantiated altera_mm_interconnect "mm_interconnect_0"]]> queue size: 143 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"]]> queue size: 141 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 126 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"]]> queue size: 124 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 123 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 92 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 91 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> queue size: 90 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> queue size: 86 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006" mm_interconnect_0" instantiated altera_merlin_router "router_006"]]> queue size: 75 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 73 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 72 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux_001" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> queue size: 71 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> queue size: 67 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 56 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 52 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"]]> queue size: 51 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"]]> queue size: 41 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 40 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux_001" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 39 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> queue size: 35 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 1 starting:error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 327 starting:altera_mm_interconnect "submodules/Qsys_mm_interconnect_1" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 22 modules, 64 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 22 modules, 64 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 22 modules, 64 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 22 modules, 64 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.006s Timing: COM:3/0.012s/0.013s 23 modules, 67 connections]]> Transform: ResetAdaptation mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router_002"]]> mm_interconnect_1" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_cmd_mux"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_rsp_demux"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux"]]> mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter"]]> Qsys" instantiated altera_mm_interconnect "mm_interconnect_1"]]> queue size: 143 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"]]> queue size: 141 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 126 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"]]> queue size: 124 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 123 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 13 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router" mm_interconnect_1" instantiated altera_merlin_router "router"]]> queue size: 11 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router_002" mm_interconnect_1" instantiated altera_merlin_router "router_002"]]> queue size: 10 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> queue size: 9 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 7 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_cmd_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 6 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_rsp_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 5 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 3 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 1 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 347 starting:altera_irq_mapper "submodules/Qsys_irq_mapper" Qsys" instantiated altera_irq_mapper "irq_mapper"]]> queue size: 346 starting:altera_reset_controller "submodules/altera_reset_controller" Qsys" instantiated altera_reset_controller "rst_controller"]]> queue size: 343 starting:alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2" alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"]]> queue size: 341 starting:alt_au "submodules/alt_cusp161_au" alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"]]> queue size: 332 starting:alt_reg "submodules/alt_cusp161_reg" alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 331 starting:alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16" alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"]]> queue size: 307 starting:alt_avalon_st_input "submodules/alt_cusp161_avalon_st_input" alt_vip_vfb_0" instantiated alt_avalon_st_input "din"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 302 starting:alt_avalon_st_output "submodules/alt_cusp161_avalon_st_output" alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 298 starting:alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo" alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 296 starting:alt_cusp_pulling_width_adapter "submodules/alt_cusp161_pulling_width_adapter" alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 290 starting:alt_cusp_pushing_width_adapter "submodules/alt_cusp161_pushing_width_adapter" alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 256 starting:alt_pc "submodules/alt_cusp161_pc" alt_vip_vfb_0" instantiated alt_pc "pc0"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 196 starting:alt_cmp "submodules/alt_cusp161_cmp" alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 146 starting:alt_cusp_testbench_clock "submodules/alt_cusp161_clock_reset" alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 144 starting:altera_nios2_gen2_unit "submodules/Qsys_nios2_gen2_cpu" Starting RTL generation for module 'Qsys_nios2_gen2_cpu' Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ] # 2021.05.27 17:51:00 (*) Starting Nios II generation # 2021.05.27 17:51:00 (*) Checking for plaintext license. # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty # 2021.05.27 17:51:01 (*) Plaintext license not found. # 2021.05.27 17:51:01 (*) Checking for encrypted license (non-evaluation). # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty # 2021.05.27 17:51:01 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF) # 2021.05.27 17:51:01 (*) Elaborating CPU configuration settings # 2021.05.27 17:51:01 (*) Creating all objects for CPU # 2021.05.27 17:51:01 (*) Testbench # 2021.05.27 17:51:02 (*) Instruction decoding # 2021.05.27 17:51:02 (*) Instruction fields # 2021.05.27 17:51:02 (*) Instruction decodes # 2021.05.27 17:51:02 (*) Signals for RTL simulation waveforms # 2021.05.27 17:51:02 (*) Instruction controls # 2021.05.27 17:51:02 (*) Pipeline frontend # 2021.05.27 17:51:02 (*) Pipeline backend # 2021.05.27 17:51:05 (*) Generating RTL from CPU objects # 2021.05.27 17:51:06 (*) Creating encrypted RTL # 2021.05.27 17:51:07 (*) Done Nios II generation Done RTL generation for module 'Qsys_nios2_gen2_cpu' nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 143 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"]]> queue size: 141 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> queue size: 126 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"]]> queue size: 124 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> queue size: 123 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> queue size: 92 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 91 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> queue size: 90 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002" mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> queue size: 86 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006" mm_interconnect_0" instantiated altera_merlin_router "router_006"]]> queue size: 75 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 73 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 72 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux_001" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> queue size: 71 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> queue size: 67 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 56 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 52 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"]]> queue size: 51 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005" mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"]]> queue size: 41 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 40 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux_001" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 39 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> queue size: 35 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 1 starting:error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 13 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router" mm_interconnect_1" instantiated altera_merlin_router "router"]]> queue size: 11 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router_002" mm_interconnect_1" instantiated altera_merlin_router "router_002"]]> queue size: 10 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> queue size: 9 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 7 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_cmd_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 6 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_rsp_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 5 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 3 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv]]> C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 1 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 1 starting:error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 0 starting:error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]>