mirror of
https://github.com/supleed2/ELEC50003-P1-CW.git
synced 2024-11-10 01:35:50 +00:00
116 lines
3.3 KiB
Tcl
116 lines
3.3 KiB
Tcl
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# TCL File Generated by Component Editor 16.1
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# Thu May 27 17:12:45 BST 2021
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# DO NOT MODIFY
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#
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# uart_interface "uart_interface" v1.0
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# 2021.05.27.17:12:45
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#
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module uart_interface
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME uart_interface
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME uart_interface
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL uart
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file uart.v VERILOG PATH ip/de10lite-hdl/uart.v TOP_LEVEL_FILE
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#
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# parameters
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#
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add_parameter CLK_FREQ INTEGER 50000000
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set_parameter_property CLK_FREQ DEFAULT_VALUE 50000000
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set_parameter_property CLK_FREQ DISPLAY_NAME CLK_FREQ
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set_parameter_property CLK_FREQ TYPE INTEGER
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set_parameter_property CLK_FREQ UNITS None
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set_parameter_property CLK_FREQ HDL_PARAMETER true
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add_parameter BAUD INTEGER 115200
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set_parameter_property BAUD DEFAULT_VALUE 115200
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set_parameter_property BAUD DISPLAY_NAME BAUD
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set_parameter_property BAUD TYPE INTEGER
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set_parameter_property BAUD UNITS None
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set_parameter_property BAUD HDL_PARAMETER true
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clock
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset reset reset Input 1
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#
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# connection point conduit_end
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#
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add_interface conduit_end conduit end
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set_interface_property conduit_end associatedClock clock
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set_interface_property conduit_end associatedReset ""
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set_interface_property conduit_end ENABLED true
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set_interface_property conduit_end EXPORT_OF ""
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set_interface_property conduit_end PORT_NAME_MAP ""
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set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
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set_interface_property conduit_end SVD_ADDRESS_GROUP ""
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add_interface_port conduit_end rx rx Input 1
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add_interface_port conduit_end rx_data rx_data Output 8
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add_interface_port conduit_end rx_valid rx_valid Output 1
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add_interface_port conduit_end tx tx Output 1
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add_interface_port conduit_end tx_data tx_data Input 8
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add_interface_port conduit_end tx_transmit tx_transmit Input 1
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add_interface_port conduit_end tx_ready tx_ready Output 1
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