mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
synced 2024-09-19 20:26:18 +00:00
685f69a7cf
Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
100 lines
3 KiB
Plaintext
100 lines
3 KiB
Plaintext
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 200 224)
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(text "mux_8x16" (rect 5 0 46 12)(font "Arial" ))
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(text "inst" (rect 8 192 20 204)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "s[2..0]" (rect 0 0 24 12)(font "Arial" ))
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(text "s[2..0]" (rect 21 27 45 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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(port
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(pt 0 48)
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(input)
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(text "in0[15..0]" (rect 21 43 55 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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(pt 0 64)
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(input)
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(text "in1[15..0]" (rect 0 0 33 12)(font "Arial" ))
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(text "in1[15..0]" (rect 21 59 54 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 3))
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)
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(port
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(input)
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(line (pt 0 80)(pt 16 80)(line_width 3))
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)
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(line (pt 0 128)(pt 16 128)(line_width 3))
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)
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(port
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(pt 0 144)
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(input)
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(text "in6[15..0]" (rect 0 0 34 12)(font "Arial" ))
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(text "in6[15..0]" (rect 21 139 55 151)(font "Arial" ))
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(line (pt 0 144)(pt 16 144)(line_width 3))
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)
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(port
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(pt 0 160)
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(input)
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(text "in7[15..0]" (rect 0 0 34 12)(font "Arial" ))
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(line (pt 0 160)(pt 16 160)(line_width 3))
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)
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(port
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(pt 184 32)
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(output)
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(text "result[15..0]" (rect 0 0 44 12)(font "Arial" ))
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(text "result[15..0]" (rect 119 27 163 39)(font "Arial" ))
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(line (pt 184 32)(pt 168 32)(line_width 3))
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)
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(drawing
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)
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)
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