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42 lines
703 B
Verilog
42 lines
703 B
Verilog
module SM
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(
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input CLK,
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input E2,
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input RST, //resets state machine to FETCH
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output FETCH,
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output EXEC1,
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output EXEC2
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);
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reg [2:0]s = 3'b1; //current state initialised to 001
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always @(posedge CLK) //Change on rising edge of clock
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begin
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case(s)
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3'b000: s = 3'b001; //if in 000, go to FETCH
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3'b001: begin
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if(!RST)
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s = 3'b010;
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else
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s = 3'b001;
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end
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3'b010: begin //if in EXEC1, go to EXEC2 if E2=1 or FETCH if E2=0
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if(!RST)
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if(E2)
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s = 3'b100;
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else
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s = 3'b001;
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else
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s = 3'b001;
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end
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3'b100: s = 3'b001; //if in EXEC2, go to FETCH
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default: s = 3'b001;
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endcase
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end
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assign FETCH = s[0];
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assign EXEC1 = s[1];
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assign EXEC2 = s[2];
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endmodule
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