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20 lines
282 B
Verilog
20 lines
282 B
Verilog
module mux_3x16 (s, in0, in1, in2, result);
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input [1:0]s;
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input [15:0]in0;
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input [15:0]in1;
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input [15:0]in2;
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output reg [15:0]result;
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always @(*) begin
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case(s)
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2'b00: result = in0;
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2'b01: result = in1;
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2'b10: result = in2;
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default: result = in0;
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endcase
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end
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endmodule
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