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73 lines
3.8 KiB
Verilog
73 lines
3.8 KiB
Verilog
module DECODE
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(
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input [15:0] instr,
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input EXEC1,
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input EXEC2,
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input COND_result,
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output R0_count,
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output R0_en,
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output R1_en,
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output R2_en,
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output R3_en,
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output R4_en,
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output R5_en,
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output R6_en,
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output R7_en,
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output [2:0] s1,
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output [2:0] s2,
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output [2:0] s3,
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output s4,
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output RAMd_wren,
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output RAMd_en,
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output RAMi_en,
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output ALU_en,
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output E2
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);
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wire msb = instr[15]; //MSB of the instruction word
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wire ls = instr[14]; //LOAD or STORE bit
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wire [2:0] Rls = instr[13:11]; //Register in the LOAD/STORE operation
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wire [10:0] addr = instr[10:0]; //Memory address in the LOAD/STORE operation
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wire [5:0] op = instr[14:9]; //Opcode in regular instructions
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wire [2:0] Rd = instr[8:6]; //Destination register in command
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wire [2:0] Rs1 = instr[5:3]; //Source register 1 in command
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wire [2:0] Rs2 = instr[2:0]; //Source register 2 in command
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//Different opcodes (refer to documentation):
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wire LOAD = msb & ~ls;
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wire STORE = msb & ls;
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wire UJMP = ~op[5] & ~op[4] & ~op[3] & ~op[2];
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wire JMP = (~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]);
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wire MUL = ~op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0];
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wire MLA = ~op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0];
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wire MLS = ~op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
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wire NOP = op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
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wire STP = op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
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assign R0_count = EXEC1 & (~(UJMP | JMP | STP));
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assign R0_en = EXEC1 & (~(STORE | NOP | STP) & ~Rd[2] & ~Rd[1] & ~Rd[0] | UJMP | JMP & COND_result) | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] & ~Rls[1] & ~Rls[0];
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assign R1_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & ~Rd[2] & ~Rd[1] & Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] & ~Rls[1] & Rls[0];
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assign R2_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & ~Rd[2] & Rd[1] & ~Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] & Rls[1] & ~Rls[0];
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assign R3_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & ~Rd[2] & Rd[1] & Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] & Rls[1] & Rls[0];
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assign R4_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & Rd[2] & ~Rd[1] & ~Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & Rls[2] & ~Rls[1] & ~Rls[0];
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assign R5_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & Rd[2] & ~Rd[1] & Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & Rls[2] & ~Rls[1] & Rls[0];
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assign R6_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & Rd[2] & Rd[1] & ~Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & Rls[2] & Rls[1] & ~Rls[0];
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assign R7_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & Rd[2] & Rd[1] & Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & Rls[2] & Rls[1] & Rls[0];
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assign s1[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[2]) | (STORE & Rls[2]));
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assign s1[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[1]) | (STORE & Rls[1]));
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assign s1[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[0]) | (STORE & Rls[0]));
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assign s2[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[2]);
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assign s2[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[1]);
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assign s2[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[0]);
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assign s3[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[2]);
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assign s3[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[1]);
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assign s3[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[0]);
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assign s4 = EXEC1 & ~(LOAD | STORE);
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assign RAMd_wren = EXEC1 & STORE;
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assign RAMd_en = EXEC1 & (STORE | LOAD);
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assign RAMi_en = EXEC1 & ~STP | EXEC2 & (LOAD | MUL | MLA | MLS);
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assign ALU_en = LOAD | STORE;
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assign E2 = EXEC1 & (LOAD | MUL | MLA | MLS);
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endmodule
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