mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
synced 2024-09-19 20:26:18 +00:00
45 lines
1.3 KiB
Plaintext
45 lines
1.3 KiB
Plaintext
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
-- Your use of Intel Corporation's design tools, logic functions
|
|
-- and other software and tools, and its AMPP partner logic
|
|
-- functions, and any output files from any of the foregoing
|
|
-- (including device programming or simulation files), and any
|
|
-- associated documentation or information are expressly subject
|
|
-- to the terms and conditions of the Intel Program License
|
|
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
-- the Intel FPGA IP License Agreement, or other applicable license
|
|
-- agreement, including, without limitation, that your use is for
|
|
-- the sole purpose of programming logic devices manufactured by
|
|
-- Intel and sold by Intel or its authorized distributors. Please
|
|
-- refer to the applicable agreement for further details.
|
|
|
|
-- Quartus Prime generated Memory Initialization File (.mif)
|
|
|
|
WIDTH=16;
|
|
DEPTH=2048;
|
|
|
|
ADDRESS_RADIX=HEX;
|
|
DATA_RADIX=HEX;
|
|
|
|
CONTENT BEGIN
|
|
000 : 0002;
|
|
001 : 0003;
|
|
002 : 0000;
|
|
003 : FFFF;
|
|
004 : BFFF;
|
|
005 : 000A;
|
|
006 : 0017;
|
|
007 : 001A;
|
|
008 : 001D;
|
|
009 : 0020;
|
|
00A : 0024;
|
|
00B : 0000;
|
|
00C : 0027;
|
|
00D : 002A;
|
|
00E : 002D;
|
|
00F : 0032;
|
|
010 : AAAA;
|
|
011 : 0004;
|
|
012 : FFF0;
|
|
[013..7FF] : 0000;
|
|
END;
|