mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
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95 lines
2.1 KiB
Plaintext
95 lines
2.1 KiB
Plaintext
-- Copyright (C) 2019 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- Quartus Prime generated Memory Initialization File (.mif)
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WIDTH=16;
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DEPTH=2048;
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ADDRESS_RADIX=UNS;
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DATA_RADIX=HEX;
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CONTENT BEGIN
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0 : 8800;
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1 : 9001;
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2 : 26D0;
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3 : 291A;
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4 : 2D20;
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5 : 3161;
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6 : 3448;
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7 : 3993;
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8 : 3AA5;
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9 : D002;
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10 : 3CE2;
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11 : A003;
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12 : 9804;
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13 : 38A5;
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14 : 3FC0;
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15 : 419D;
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16 : 304F;
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17 : 5008;
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18 : 5028;
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19 : 284F;
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20 : 43F1;
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21 : 3568;
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22 : 45F5;
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23 : 484D;
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24 : 8806;
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25 : 0040;
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26 : B800;
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27 : 8807;
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28 : 085A;
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29 : B800;
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30 : 8808;
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31 : 0A6F;
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32 : B800;
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33 : 8809;
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34 : 0C53;
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35 : B801;
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36 : 880A;
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37 : B00B;
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38 : 0E70;
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39 : B800;
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40 : 880C;
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41 : 1063;
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42 : B800;
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43 : 880D;
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44 : 126D;
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45 : B800;
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46 : 880E;
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47 : 147A;
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48 : B800;
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49 : 880F;
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50 : 5340;
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51 : 53C0;
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52 : 1660;
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53 : B801;
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54 : 1863;
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55 : 1A5A;
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56 : 1FB8;
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57 : 7C00;
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58 : 1C6F;
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59 : 204C;
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60 : A810;
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61 : 226D;
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62 : 246D;
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63 : 8805;
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64 : 5488;
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65 : 5698;
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66 : A028;
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67 : 7E00;
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[68..2047] : 0000;
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END;
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