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11 lines
222 B
Verilog
11 lines
222 B
Verilog
module max_min(a, b, maximum, minimum);
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input unsigned [7:0] a;
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input unsigned [7:0] b;
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output unsigned [7:0] maximum;
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output unsigned [7:0] minimum;
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assign minimum = (a<b) ? a:b;
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assign maximum = (a>b) ? a:b;
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endmodule |