mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
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114 lines
3.8 KiB
Plaintext
114 lines
3.8 KiB
Plaintext
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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*/
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(header "symbol" (version "1.2"))
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(symbol
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(rect 16 16 264 208)
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(text "ALU_top" (rect 5 0 56 19)(font "Intel Clear" (font_size 8)))
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(text "inst" (rect 8 171 24 188)(font "Intel Clear" ))
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(port
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(pt 0 32)
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(input)
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(text "ALU_en" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
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(text "ALU_en" (rect 21 27 67 46)(font "Intel Clear" (font_size 8)))
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(line (pt 0 32)(pt 16 32))
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)
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(port
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(pt 0 48)
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(input)
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(text "Rs1[15..0]" (rect 0 0 61 19)(font "Intel Clear" (font_size 8)))
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(text "Rs1[15..0]" (rect 21 43 82 62)(font "Intel Clear" (font_size 8)))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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(pt 0 64)
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(input)
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(text "Rs2[15..0]" (rect 0 0 61 19)(font "Intel Clear" (font_size 8)))
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(text "Rs2[15..0]" (rect 21 59 82 78)(font "Intel Clear" (font_size 8)))
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(line (pt 0 64)(pt 16 64)(line_width 3))
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)
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(port
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(pt 0 80)
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(input)
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(text "Rd[15..0]" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
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(text "Rd[15..0]" (rect 21 75 76 94)(font "Intel Clear" (font_size 8)))
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(line (pt 0 80)(pt 16 80)(line_width 3))
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)
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(port
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(pt 0 96)
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(input)
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(text "op[5..0]" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
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(text "op[5..0]" (rect 21 91 67 110)(font "Intel Clear" (font_size 8)))
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(line (pt 0 96)(pt 16 96)(line_width 3))
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)
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(port
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(pt 0 112)
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(input)
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(text "EXEC2" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
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(text "EXEC2" (rect 21 107 59 126)(font "Intel Clear" (font_size 8)))
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(line (pt 0 112)(pt 16 112))
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)
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(port
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(pt 0 128)
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(input)
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(text "stack_data[15..0]" (rect 0 0 103 19)(font "Intel Clear" (font_size 8)))
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(text "stack_data[15..0]" (rect 21 123 124 142)(font "Intel Clear" (font_size 8)))
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(line (pt 0 128)(pt 16 128)(line_width 3))
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)
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(port
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(pt 0 144)
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(input)
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(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
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(text "CLK" (rect 21 139 44 158)(font "Intel Clear" (font_size 8)))
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(line (pt 0 144)(pt 16 144))
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)
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(port
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(pt 248 32)
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(output)
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(text "Rout[15..0]" (rect 0 0 66 19)(font "Intel Clear" (font_size 8)))
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(text "Rout[15..0]" (rect 161 27 227 46)(font "Intel Clear" (font_size 8)))
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(line (pt 248 32)(pt 232 32)(line_width 3))
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)
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(port
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(pt 248 48)
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(output)
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(text "COND" (rect 0 0 36 19)(font "Intel Clear" (font_size 8)))
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(text "COND" (rect 191 43 227 62)(font "Intel Clear" (font_size 8)))
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(line (pt 248 48)(pt 232 48))
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)
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(port
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(pt 248 64)
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(output)
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(text "CARRY" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
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(text "CARRY" (rect 186 59 227 78)(font "Intel Clear" (font_size 8)))
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(line (pt 248 64)(pt 232 64))
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)
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(port
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(pt 248 80)
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(output)
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(text "MUL_res[31..0]" (rect 0 0 90 19)(font "Intel Clear" (font_size 8)))
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(text "MUL_res[31..0]" (rect 137 75 227 94)(font "Intel Clear" (font_size 8)))
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(line (pt 248 80)(pt 232 80)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 232 176))
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)
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)
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