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30 lines
516 B
Verilog
30 lines
516 B
Verilog
module mux_8x16 (s, in0, in1, in2, in3, in4, in5, in6, in7, result);
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input [2:0]s;
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input [15:0]in0;
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input [15:0]in1;
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input [15:0]in2;
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input [15:0]in3;
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input [15:0]in4;
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input [15:0]in5;
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input [15:0]in6;
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input [15:0]in7;
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output reg [15:0]result;
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always @(*) begin
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case(s)
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3'b000: result = in0;
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3'b001: result = in1;
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3'b010: result = in2;
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3'b011: result = in3;
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3'b100: result = in4;
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3'b101: result = in5;
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3'b110: result = in6;
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3'b111: result = in7;
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default: result = in0;
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endcase
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end
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endmodule
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