mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
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685f69a7cf
Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
86 lines
2.6 KiB
Plaintext
86 lines
2.6 KiB
Plaintext
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 200 160)
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(text "LIFOstack" (rect 5 0 47 12)(font "Arial" ))
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(port
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