-- Copyright (C) 2019  Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions 
-- and other software and tools, and any partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Intel Program License 
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors.  Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.

-- Quartus Prime generated Memory Initialization File (.mif)

WIDTH=16;
DEPTH=2048;

ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;

CONTENT BEGIN
	000  :   0002;
	001  :   0003;
	002  :   0000;
	003  :   FFFF;
	004  :   BFFF;
	005  :   000A;
	006  :   001B;
	007  :   001E;
	008  :   0021;
	009  :   0024;
	00A  :   0028;
	00B  :   0000;
	00C  :   002B;
	00D  :   002E;
	00E  :   0031;
	00F  :   0036;
	010  :   AAAA;
	[011..7FF]  :   0000;
END;