/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
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		(line (pt 145 144)(pt 160 144))
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		"LPM_DIRECTION"
		"\"ADD\""
		"Selects between addition, subtraction, or both"
		"\"DEFAULT\"" "\"ADD\"" "\"SUB\"" 
		(type "PARAMETER_UNKNOWN")	)
	(parameter
		"LPM_PIPELINE"
		""
		"Output latency in clock cycles - requires use of optional clock"
		"0" "1" "2" "3" "4" 
	)
	(parameter
		"LPM_REPRESENTATION"
		"\"UNSIGNED\""
		"Numeric representation of inputs"
		"\"UNSIGNED\"" "\"SIGNED\"" 
		(type "PARAMETER_UNKNOWN")	)
	(parameter
		"LPM_WIDTH"
		"32"
		"Width of I/O, any integer > 0"
		" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64" 
		(type "PARAMETER_UNSIGNED_DEC")	)
	(parameter
		"MAXIMIZE_SPEED"
		""
		"Hint to help tradeoff between speed and size"
		" 0" " 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" 
	)
	(parameter
		"ONE_INPUT_IS_CONSTANT"
		""
		"Hint to help minimize the number of LCELLs"
		"\"NO\"" "\"YES\"" 
	)
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		(line (pt 145 96)(pt 160 96)(line_width 3))
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	(parameter
		"LPM_DIRECTION"
		"\"ADD\""
		"Selects between addition, subtraction, or both"
		"\"DEFAULT\"" "\"ADD\"" "\"SUB\"" 
		(type "PARAMETER_UNKNOWN")	)
	(parameter
		"LPM_PIPELINE"
		""
		"Output latency in clock cycles - requires use of optional clock"
		"0" "1" "2" "3" "4" 
	)
	(parameter
		"LPM_REPRESENTATION"
		"\"UNSIGNED\""
		"Numeric representation of inputs"
		"\"UNSIGNED\"" "\"SIGNED\"" 
		(type "PARAMETER_UNKNOWN")	)
	(parameter
		"LPM_WIDTH"
		"32"
		"Width of I/O, any integer > 0"
		" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64" 
		(type "PARAMETER_UNSIGNED_DEC")	)
	(parameter
		"MAXIMIZE_SPEED"
		""
		"Hint to help tradeoff between speed and size"
		" 0" " 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" 
	)
	(parameter
		"ONE_INPUT_IS_CONSTANT"
		""
		"Hint to help minimize the number of LCELLs"
		"\"NO\"" "\"YES\"" 
	)
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		(line (pt 145 144)(pt 160 144))
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		(text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
		(line (pt 145 96)(pt 160 96)(line_width 3))
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	(parameter
		"LPM_DIRECTION"
		"\"ADD\""
		"Selects between addition, subtraction, or both"
		"\"DEFAULT\"" "\"ADD\"" "\"SUB\"" 
		(type "PARAMETER_UNKNOWN")	)
	(parameter
		"LPM_PIPELINE"
		""
		"Output latency in clock cycles - requires use of optional clock"
		"0" "1" "2" "3" "4" 
	)
	(parameter
		"LPM_REPRESENTATION"
		"\"UNSIGNED\""
		"Numeric representation of inputs"
		"\"UNSIGNED\"" "\"SIGNED\"" 
		(type "PARAMETER_UNKNOWN")	)
	(parameter
		"LPM_WIDTH"
		"32"
		"Width of I/O, any integer > 0"
		" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64" 
		(type "PARAMETER_UNSIGNED_DEC")	)
	(parameter
		"MAXIMIZE_SPEED"
		""
		"Hint to help tradeoff between speed and size"
		" 0" " 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" 
	)
	(parameter
		"ONE_INPUT_IS_CONSTANT"
		""
		"Hint to help minimize the number of LCELLs"
		"\"NO\"" "\"YES\"" 
	)
	(drawing
		(line (pt 16 48)(pt 72 48))
		(line (pt 16 152)(pt 144 152))
		(line (pt 16 16)(pt 144 16))
		(line (pt 16 72)(pt 56 72)(line_width 3))
		(line (pt 16 120)(pt 56 120)(line_width 3))
		(line (pt 104 96)(pt 144 96)(line_width 3))
		(line (pt 88 128)(pt 144 128))
		(line (pt 16 32)(pt 88 32))
		(line (pt 80 144)(pt 144 144))
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		(line (pt 104 112)(pt 104 80))
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	(pt 648 336)
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	(pt 576 352)
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	(pt 648 440)
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	(text "B[7..0]" (rect 594 440 624 457)(font "Intel Clear" ))
	(pt 648 456)
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	(pt 816 104)
	(pt 880 104)
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	(text "P2[15..0]" (rect 826 208 868 225)(font "Intel Clear" ))
	(pt 816 224)
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(connector
	(text "P3[15..0]" (rect 826 320 868 337)(font "Intel Clear" ))
	(pt 816 336)
	(pt 888 336)
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(connector
	(text "P4[15..0]" (rect 826 424 868 441)(font "Intel Clear" ))
	(pt 816 440)
	(pt 888 440)
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)
(connector
	(text "P[31..0]" (rect 1738 264 1774 281)(font "Intel Clear" ))
	(pt 1728 280)
	(pt 1872 280)
	(bus)
)