From 2ca1e90a2cb4ae190e9f31b81afab905cc094e39 Mon Sep 17 00:00:00 2001
From: supleed2 <21363892+supleed2@users.noreply.github.com>
Date: Tue, 2 Jun 2020 16:57:58 +0100
Subject: [PATCH 1/3] ALU enable control added, minor fix with RRC

Multiply still to be updated
---
 alu.v | 147 ++++++++++++++++++++++++++++++----------------------------
 1 file changed, 77 insertions(+), 70 deletions(-)

diff --git a/alu.v b/alu.v
index d813cc6..1389477 100644
--- a/alu.v
+++ b/alu.v
@@ -36,76 +36,83 @@ assign JC8 = (Rs1 < 0);
 
 always @(*)
 	begin
-		case (opcode)
-			6'b000000: alusum = {1'b1, Rd}; // JMP Unconditional Jump, first bit high to indicate jump and passes through Rd
-			
-			6'b000100: alusum = {JC1, Rd}; // JC1 Conditional Jump A < B
-			6'b000101: alusum = {JC2, Rd}; // JC2 Conditional Jump A > B
-			6'b000110: alusum = {JC3, Rd}; // JC3 Conditional Jump A = B
-			6'b000111: alusum = {JC4, Rd}; // JC4 Conditional Jump A = 0
-			
-			6'b001000: alusum = {JC5, Rd}; // JC5 Conditional Jump A >= B / A !< B
-			6'b001001: alusum = {JC6, Rd}; // JC6 Conditional Jump A <= B / A !> B
-			6'b001010: alusum = {JC7, Rd}; // JC7 Conditional Jump A != B
-			6'b001011: alusum = {JC8, Rd}; // JC8 Conditional Jump A < 0
-			
-			6'b001100: alusum = {1'b0, Rs1 & Rs2}; // AND Bitwise AND
-			6'b001101: alusum = {1'b0, Rs1 | Rs2}; // OR Bitwise OR
-			6'b001110: alusum = {1'b0, Rs1 ^ Rs2}; // XOR Bitwise XOR
-			6'b001111: alusum = {1'b0, ~Rs1}; // NOT Bitwise NOT
-			
-			6'b010000: alusum = {1'b0, ~Rs1 | ~Rs2}; // NND Bitwise NAND
-			6'b010001: alusum = {1'b0, ~Rs1 & ~Rs2}; // NOR Bitwise NOR
-			6'b010010: alusum = {1'b0, Rs1 ~^ Rs2}; // XNR Bitwise XNOR
-			6'b010011: alusum = {1'b0, Rs1}; // MOV Move (Rd = Rs1)
-			
-			6'b010100: alusum = {1'b0, Rs1} + {1'b0, Rs2}; // ADD Add (Rd = Rs1 + Rs2)
-			6'b010101: alusum = {1'b0, Rs1} + {1'b0, Rs2} + carryin; // ADC Add w/ Carry (Rd = Rs1 + Rs2 + C)
-			6'b010110: alusum = {1'b0, Rs1} + {17'b00000000000000001}; // ADO Add 1 (Rd = Rd + 1)
-			6'b010111: ;
-			
-			6'b011000: alusum = {1'b0, Rs1} - {1'b0, Rs2}; // SUB Subtract (Rd = Rs1 - Rs2)
-			6'b011001: alusum = {1'b0, Rs1} - {1'b0, Rs2} + carryin - {17'b00000000000000001}; // SBC Subtract w/ Carry (Rd = Rs1 - Rs2 + C - 1)
-			6'b011010: alusum = {1'b0, Rs1} - {17'b00000000000000001}; // SBO Subtract 1 (Rd = Rd - 1)
-			6'b011011: ;
-			
-			6'b011100: // MUL Multiply (Rd = Rs1 * Rs2)
-				begin
-//					mul1 = Rs1;
-//					mul2 = Rs2;
-					alusum[16] = 1'b0;
-					{mulextra, alusum[15:0]} = Rs1 * Rs2;
-				end
-			6'b011101: // MLA Multiply and Add  (Rd = Rs2 + (Rd * Rs1))
-				begin
-//					mul1 = Rs1;
-//					mul2 = Rs2;
-					alusum[16] = 1'b0;
-					{mulextra, alusum[15:0]} = (Rd * Rs1) + Rs2;
-				end
-			6'b011110: // MLS Multiply and Subtract (Rd = Rs2 - (Rd * Rs1)[15:0])
-				begin
-//					mul1 = Rs1;
-//					mul2 = Rs2;
-					alusum = {1'b0, Rs2 - (Rd * Rs1)};
-				end
-			6'b011111: alusum = mulextra; // MRT Retrieve Multiply MSBs (Rd = MSBs)
-			
-			6'b100000: alusum = {1'b0, Rs1 << Rs2}; // LSL Logical Shift Left (Rd = Rs1 shifted left by value of Rs2)
-			6'b100001: alusum = {1'b0, Rs1 >> Rs2}; // LSR Logical Shift Right (Rd = Rs1 shifted right by value of Rs2)
-			6'b100010: alusum = {Rs1[15], Rs1 >>> Rs2}; // ASR Arithmetic Shift Right (Rd = Rs1 shifted right by value of Rs2, maintaining sign bit)
-			6'b100011: ;
-			
-			6'b100100: alusum = {1'b0, (Rs1 >> Rs2[3:0]) | (Rs1 << (16 - Rs2[3:0]))}; // ROR Shift Right Loop (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Rs1[15])
-			6'b100101: alusum = ({Rs1, carryin} >> Rs2[3:0]) | ({Rs1, carryin} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
-			6'b100110: ;
-			6'b100111: ;
-			
-			6'b111110: ; // NOP No Operation (Do Nothing for a cycle)
-			6'b111111: ; // STP Stop (Program Ends)
-			
-			default: ; // During Load & Store as well as undefined opcodes
-		endcase;
+		if(!enable)
+			begin
+			case (opcode)
+				6'b000000: alusum = {1'b1, Rd}; // JMP Unconditional Jump, first bit high to indicate jump and passes through Rd
+				
+				6'b000100: alusum = {JC1, Rd}; // JC1 Conditional Jump A < B
+				6'b000101: alusum = {JC2, Rd}; // JC2 Conditional Jump A > B
+				6'b000110: alusum = {JC3, Rd}; // JC3 Conditional Jump A = B
+				6'b000111: alusum = {JC4, Rd}; // JC4 Conditional Jump A = 0
+				
+				6'b001000: alusum = {JC5, Rd}; // JC5 Conditional Jump A >= B / A !< B
+				6'b001001: alusum = {JC6, Rd}; // JC6 Conditional Jump A <= B / A !> B
+				6'b001010: alusum = {JC7, Rd}; // JC7 Conditional Jump A != B
+				6'b001011: alusum = {JC8, Rd}; // JC8 Conditional Jump A < 0
+				
+				6'b001100: alusum = {1'b0, Rs1 & Rs2}; // AND Bitwise AND
+				6'b001101: alusum = {1'b0, Rs1 | Rs2}; // OR Bitwise OR
+				6'b001110: alusum = {1'b0, Rs1 ^ Rs2}; // XOR Bitwise XOR
+				6'b001111: alusum = {1'b0, ~Rs1}; // NOT Bitwise NOT
+				
+				6'b010000: alusum = {1'b0, ~Rs1 | ~Rs2}; // NND Bitwise NAND
+				6'b010001: alusum = {1'b0, ~Rs1 & ~Rs2}; // NOR Bitwise NOR
+				6'b010010: alusum = {1'b0, Rs1 ~^ Rs2}; // XNR Bitwise XNOR
+				6'b010011: alusum = {1'b0, Rs1}; // MOV Move (Rd = Rs1)
+				
+				6'b010100: alusum = {1'b0, Rs1} + {1'b0, Rs2}; // ADD Add (Rd = Rs1 + Rs2)
+				6'b010101: alusum = {1'b0, Rs1} + {1'b0, Rs2} + carryin; // ADC Add w/ Carry (Rd = Rs1 + Rs2 + C)
+				6'b010110: alusum = {1'b0, Rs1} + {17'b00000000000000001}; // ADO Add 1 (Rd = Rd + 1)
+				6'b010111: ;
+				
+				6'b011000: alusum = {1'b0, Rs1} - {1'b0, Rs2}; // SUB Subtract (Rd = Rs1 - Rs2)
+				6'b011001: alusum = {1'b0, Rs1} - {1'b0, Rs2} + carryin - {17'b00000000000000001}; // SBC Subtract w/ Carry (Rd = Rs1 - Rs2 + C - 1)
+				6'b011010: alusum = {1'b0, Rs1} - {17'b00000000000000001}; // SBO Subtract 1 (Rd = Rd - 1)
+				6'b011011: ;
+				
+				6'b011100: // MUL Multiply (Rd = Rs1 * Rs2)
+					begin
+//						mul1 = Rs1;
+//						mul2 = Rs2;
+						alusum[16] = 1'b0;
+						{mulextra, alusum[15:0]} = Rs1 * Rs2;
+					end
+				6'b011101: // MLA Multiply and Add  (Rd = Rs2 + (Rd * Rs1))
+					begin
+//						mul1 = Rs1;
+//						mul2 = Rs2;
+						alusum[16] = 1'b0;
+						{mulextra, alusum[15:0]} = (Rd * Rs1) + Rs2;
+					end
+				6'b011110: // MLS Multiply and Subtract (Rd = Rs2 - (Rd * Rs1)[15:0])
+					begin
+//						mul1 = Rs1;
+//						mul2 = Rs2;
+						alusum = {1'b0, Rs2 - (Rd * Rs1)};
+					end
+				6'b011111: alusum = mulextra; // MRT Retrieve Multiply MSBs (Rd = MSBs)
+				
+				6'b100000: alusum = {1'b0, Rs1 << Rs2}; // LSL Logical Shift Left (Rd = Rs1 shifted left by value of Rs2)
+				6'b100001: alusum = {1'b0, Rs1 >> Rs2}; // LSR Logical Shift Right (Rd = Rs1 shifted right by value of Rs2)
+				6'b100010: alusum = {Rs1[15], Rs1 >>> Rs2}; // ASR Arithmetic Shift Right (Rd = Rs1 shifted right by value of Rs2, maintaining sign bit)
+				6'b100011: ;
+				
+				6'b100100: alusum = {1'b0, (Rs1 >> Rs2[3:0]) | (Rs1 << (16 - Rs2[3:0]))}; // ROR Shift Right Loop (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Rs1[15])
+				6'b100101: alusum = ({Rs1, carryin} >> (Rs2 % 17)) | ({Rs1, carryin} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
+				6'b100110: ;
+				6'b100111: ;
+				
+				6'b111110: ; // NOP No Operation (Do Nothing for a cycle)
+				6'b111111: ; // STP Stop (Program Ends)
+				
+				default: ; // During Load & Store as well as undefined opcodes
+			endcase;
+			end
+		else
+			begin
+				alusum = {1'b0, 16'h0000}; // Bring output low during Load/Store so it does not interfere
+			end
 	end
 
 /*	

From 1c0032fa95ac84509ca1e042a9b7d7b1df001c9e Mon Sep 17 00:00:00 2001
From: Kacper <kacper.neumann19@imperial.ac.uk>
Date: Tue, 2 Jun 2020 20:09:22 +0100
Subject: [PATCH 2/3] Fixed decoder and SM

---
 CPUProject.bdf | 656 +++++++++++++++++++++++++++----------------------
 CPUProject.qsf |   7 +-
 DECODE.bsf     |  35 ++-
 DECODE.v       |  75 +++---
 DECODE.v.bak   |  88 +++++++
 SM.bdf         | 283 ---------------------
 SM.bsf         |  48 ++--
 SM.v           |  22 ++
 SM.v.bak       |  22 ++
 9 files changed, 587 insertions(+), 649 deletions(-)
 create mode 100644 DECODE.v.bak
 delete mode 100644 SM.bdf
 create mode 100644 SM.v
 create mode 100644 SM.v.bak

diff --git a/CPUProject.bdf b/CPUProject.bdf
index 65217ab..8a35dc3 100644
--- a/CPUProject.bdf
+++ b/CPUProject.bdf
@@ -709,35 +709,6 @@ refer to the applicable agreement for further details.
 	)
 	(annotation_block (parameter)(rect 856 -120 888 -104))
 )
-(symbol
-	(rect 256 24 376 120)
-	(text "SM" (rect 5 0 23 19)(font "Intel Clear" (font_size 8)))
-	(text "STATE_M" (rect 8 75 54 92)(font "Intel Clear" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
-		(text "CLK" (rect 21 27 44 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 32)(pt 16 32))
-	)
-	(port
-		(pt 120 32)
-		(output)
-		(text "FETCH" (rect 0 0 40 19)(font "Intel Clear" (font_size 8)))
-		(text "FETCH" (rect 59 27 99 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 120 32)(pt 104 32))
-	)
-	(port
-		(pt 120 48)
-		(output)
-		(text "EXEC" (rect 0 0 30 19)(font "Intel Clear" (font_size 8)))
-		(text "EXEC" (rect 69 43 99 62)(font "Intel Clear" (font_size 8)))
-		(line (pt 120 48)(pt 104 48))
-	)
-	(drawing
-		(rectangle (rect 16 16 104 80))
-	)
-)
 (symbol
 	(rect 256 -144 472 0)
 	(text "ram_instr" (rect 81 0 144 16)(font "Arial" (font_size 10)))
@@ -829,147 +800,6 @@ refer to the applicable agreement for further details.
 		(line (pt 0 0)(pt 0 0))
 	)
 )
-(symbol
-	(rect 968 -152 1176 152)
-	(text "DECODE" (rect 5 0 52 12)(font "Arial" ))
-	(text "DECODE" (rect 8 288 55 300)(font "Arial" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "instr[15..0]" (rect 0 0 53 12)(font "Arial" ))
-		(text "instr[15..0]" (rect 21 27 74 39)(font "Arial" ))
-		(line (pt 0 32)(pt 16 32)(line_width 3))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "EXEC" (rect 0 0 28 12)(font "Arial" ))
-		(text "EXEC" (rect 21 43 49 55)(font "Arial" ))
-		(line (pt 0 48)(pt 16 48))
-	)
-	(port
-		(pt 0 64)
-		(input)
-		(text "COND_result" (rect 0 0 66 12)(font "Arial" ))
-		(text "COND_result" (rect 21 59 87 71)(font "Arial" ))
-		(line (pt 0 64)(pt 16 64))
-	)
-	(port
-		(pt 208 32)
-		(output)
-		(text "R0_count" (rect 0 0 47 12)(font "Arial" ))
-		(text "R0_count" (rect 148 27 187 39)(font "Arial" ))
-		(line (pt 208 32)(pt 192 32))
-	)
-	(port
-		(pt 208 48)
-		(output)
-		(text "R0_en" (rect 0 0 31 12)(font "Arial" ))
-		(text "R0_en" (rect 161 43 187 55)(font "Arial" ))
-		(line (pt 208 48)(pt 192 48))
-	)
-	(port
-		(pt 208 64)
-		(output)
-		(text "R1_en" (rect 0 0 31 12)(font "Arial" ))
-		(text "R1_en" (rect 161 59 187 71)(font "Arial" ))
-		(line (pt 208 64)(pt 192 64))
-	)
-	(port
-		(pt 208 80)
-		(output)
-		(text "R2_en" (rect 0 0 31 12)(font "Arial" ))
-		(text "R2_en" (rect 161 75 187 87)(font "Arial" ))
-		(line (pt 208 80)(pt 192 80))
-	)
-	(port
-		(pt 208 96)
-		(output)
-		(text "R3_en" (rect 0 0 31 12)(font "Arial" ))
-		(text "R3_en" (rect 161 91 187 103)(font "Arial" ))
-		(line (pt 208 96)(pt 192 96))
-	)
-	(port
-		(pt 208 112)
-		(output)
-		(text "R4_en" (rect 0 0 31 12)(font "Arial" ))
-		(text "R4_en" (rect 161 107 187 119)(font "Arial" ))
-		(line (pt 208 112)(pt 192 112))
-	)
-	(port
-		(pt 208 128)
-		(output)
-		(text "R5_en" (rect 0 0 31 12)(font "Arial" ))
-		(text "R5_en" (rect 161 123 187 135)(font "Arial" ))
-		(line (pt 208 128)(pt 192 128))
-	)
-	(port
-		(pt 208 144)
-		(output)
-		(text "R6_en" (rect 0 0 31 12)(font "Arial" ))
-		(text "R6_en" (rect 161 139 187 151)(font "Arial" ))
-		(line (pt 208 144)(pt 192 144))
-	)
-	(port
-		(pt 208 160)
-		(output)
-		(text "R7_en" (rect 0 0 31 12)(font "Arial" ))
-		(text "R7_en" (rect 161 155 187 167)(font "Arial" ))
-		(line (pt 208 160)(pt 192 160))
-	)
-	(port
-		(pt 208 176)
-		(output)
-		(text "s1[2..0]" (rect 0 0 37 12)(font "Arial" ))
-		(text "s1[2..0]" (rect 156 171 187 183)(font "Arial" ))
-		(line (pt 208 176)(pt 192 176)(line_width 3))
-	)
-	(port
-		(pt 208 192)
-		(output)
-		(text "s2[2..0]" (rect 0 0 37 12)(font "Arial" ))
-		(text "s2[2..0]" (rect 156 187 187 199)(font "Arial" ))
-		(line (pt 208 192)(pt 192 192)(line_width 3))
-	)
-	(port
-		(pt 208 208)
-		(output)
-		(text "s3[2..0]" (rect 0 0 37 12)(font "Arial" ))
-		(text "s3[2..0]" (rect 156 203 187 215)(font "Arial" ))
-		(line (pt 208 208)(pt 192 208)(line_width 3))
-	)
-	(port
-		(pt 208 224)
-		(output)
-		(text "s4" (rect 0 0 11 12)(font "Arial" ))
-		(text "s4" (rect 178 219 187 231)(font "Arial" ))
-		(line (pt 208 224)(pt 192 224))
-	)
-	(port
-		(pt 208 240)
-		(output)
-		(text "RAMd_wren" (rect 0 0 57 12)(font "Arial" ))
-		(text "RAMd_wren" (rect 139 235 187 247)(font "Arial" ))
-		(line (pt 208 240)(pt 192 240))
-	)
-	(port
-		(pt 208 256)
-		(output)
-		(text "RAMd_en" (rect 0 0 47 12)(font "Arial" ))
-		(text "RAMd_en" (rect 148 251 187 263)(font "Arial" ))
-		(line (pt 208 256)(pt 192 256))
-	)
-	(port
-		(pt 208 272)
-		(output)
-		(text "RAMi_en" (rect 0 0 43 12)(font "Arial" ))
-		(text "RAMi_en" (rect 151 267 187 279)(font "Arial" ))
-		(line (pt 208 272)(pt 192 272))
-	)
-	(drawing
-		(rectangle (rect 16 16 192 288))
-	)
-)
 (symbol
 	(rect 1024 304 1136 352)
 	(text "LPM_CONSTANT" (rect 4 0 125 16)(font "Arial" (font_size 10)))
@@ -1109,6 +939,211 @@ refer to the applicable agreement for further details.
 		(line (pt 0 0)(pt 0 0))
 	)
 )
+(symbol
+	(rect 256 16 408 128)
+	(text "SM" (rect 5 0 20 12)(font "Arial" ))
+	(text "SM" (rect 8 96 23 113)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLK" (rect 0 0 21 12)(font "Arial" ))
+		(text "CLK" (rect 21 27 42 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "E2" (rect 0 0 12 12)(font "Arial" ))
+		(text "E2" (rect 21 43 33 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 152 32)
+		(output)
+		(text "FETCH" (rect 0 0 36 12)(font "Arial" ))
+		(text "FETCH" (rect 101 27 137 39)(font "Arial" ))
+		(line (pt 152 32)(pt 136 32))
+	)
+	(port
+		(pt 152 48)
+		(output)
+		(text "EXEC1" (rect 0 0 34 12)(font "Arial" ))
+		(text "EXEC1" (rect 103 43 137 55)(font "Arial" ))
+		(line (pt 152 48)(pt 136 48))
+	)
+	(port
+		(pt 152 64)
+		(output)
+		(text "EXEC2" (rect 0 0 34 12)(font "Arial" ))
+		(text "EXEC2" (rect 103 59 137 71)(font "Arial" ))
+		(line (pt 152 64)(pt 136 64))
+	)
+	(drawing
+		(rectangle (rect 16 16 136 96))
+	)
+)
+(symbol
+	(rect 968 -184 1176 152)
+	(text "DECODE" (rect 5 0 52 12)(font "Arial" ))
+	(text "DECODE" (rect 8 320 55 332)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "instr[15..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "instr[15..0]" (rect 21 27 74 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "EXEC1" (rect 0 0 34 12)(font "Arial" ))
+		(text "EXEC1" (rect 21 43 55 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "EXEC2" (rect 0 0 34 12)(font "Arial" ))
+		(text "EXEC2" (rect 21 59 55 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "COND_result" (rect 0 0 66 12)(font "Arial" ))
+		(text "COND_result" (rect 21 75 87 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 208 32)
+		(output)
+		(text "R0_count" (rect 0 0 47 12)(font "Arial" ))
+		(text "R0_count" (rect 148 27 187 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32))
+	)
+	(port
+		(pt 208 48)
+		(output)
+		(text "R0_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R0_en" (rect 161 43 187 55)(font "Arial" ))
+		(line (pt 208 48)(pt 192 48))
+	)
+	(port
+		(pt 208 64)
+		(output)
+		(text "R1_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R1_en" (rect 161 59 187 71)(font "Arial" ))
+		(line (pt 208 64)(pt 192 64))
+	)
+	(port
+		(pt 208 80)
+		(output)
+		(text "R2_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R2_en" (rect 161 75 187 87)(font "Arial" ))
+		(line (pt 208 80)(pt 192 80))
+	)
+	(port
+		(pt 208 96)
+		(output)
+		(text "R3_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R3_en" (rect 161 91 187 103)(font "Arial" ))
+		(line (pt 208 96)(pt 192 96))
+	)
+	(port
+		(pt 208 112)
+		(output)
+		(text "R4_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R4_en" (rect 161 107 187 119)(font "Arial" ))
+		(line (pt 208 112)(pt 192 112))
+	)
+	(port
+		(pt 208 128)
+		(output)
+		(text "R5_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R5_en" (rect 161 123 187 135)(font "Arial" ))
+		(line (pt 208 128)(pt 192 128))
+	)
+	(port
+		(pt 208 144)
+		(output)
+		(text "R6_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R6_en" (rect 161 139 187 151)(font "Arial" ))
+		(line (pt 208 144)(pt 192 144))
+	)
+	(port
+		(pt 208 160)
+		(output)
+		(text "R7_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R7_en" (rect 161 155 187 167)(font "Arial" ))
+		(line (pt 208 160)(pt 192 160))
+	)
+	(port
+		(pt 208 176)
+		(output)
+		(text "s1[2..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "s1[2..0]" (rect 156 171 187 183)(font "Arial" ))
+		(line (pt 208 176)(pt 192 176)(line_width 3))
+	)
+	(port
+		(pt 208 192)
+		(output)
+		(text "s2[2..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "s2[2..0]" (rect 156 187 187 199)(font "Arial" ))
+		(line (pt 208 192)(pt 192 192)(line_width 3))
+	)
+	(port
+		(pt 208 208)
+		(output)
+		(text "s3[2..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "s3[2..0]" (rect 156 203 187 215)(font "Arial" ))
+		(line (pt 208 208)(pt 192 208)(line_width 3))
+	)
+	(port
+		(pt 208 224)
+		(output)
+		(text "s4" (rect 0 0 11 12)(font "Arial" ))
+		(text "s4" (rect 178 219 187 231)(font "Arial" ))
+		(line (pt 208 224)(pt 192 224))
+	)
+	(port
+		(pt 208 240)
+		(output)
+		(text "RAMd_wren" (rect 0 0 57 12)(font "Arial" ))
+		(text "RAMd_wren" (rect 139 235 187 247)(font "Arial" ))
+		(line (pt 208 240)(pt 192 240))
+	)
+	(port
+		(pt 208 256)
+		(output)
+		(text "RAMd_en" (rect 0 0 47 12)(font "Arial" ))
+		(text "RAMd_en" (rect 148 251 187 263)(font "Arial" ))
+		(line (pt 208 256)(pt 192 256))
+	)
+	(port
+		(pt 208 272)
+		(output)
+		(text "RAMi_en" (rect 0 0 43 12)(font "Arial" ))
+		(text "RAMi_en" (rect 151 267 187 279)(font "Arial" ))
+		(line (pt 208 272)(pt 192 272))
+	)
+	(port
+		(pt 208 288)
+		(output)
+		(text "ALU_en" (rect 0 0 38 12)(font "Arial" ))
+		(text "ALU_en" (rect 155 283 187 295)(font "Arial" ))
+		(line (pt 208 288)(pt 192 288))
+	)
+	(port
+		(pt 208 304)
+		(output)
+		(text "E2" (rect 0 0 12 12)(font "Arial" ))
+		(text "E2" (rect 177 299 187 311)(font "Arial" ))
+		(line (pt 208 304)(pt 192 304))
+	)
+	(drawing
+		(rectangle (rect 16 16 192 320))
+	)
+)
 (connector
 	(pt 504 416)
 	(pt 632 416)
@@ -1371,11 +1406,6 @@ refer to the applicable agreement for further details.
 	(pt 744 -56)
 	(bus)
 )
-(connector
-	(text "EXEC" (rect 783 -28 800 -3)(font "Intel Clear" )(vertical))
-	(pt 800 -32)
-	(pt 800 0)
-)
 (connector
 	(pt 448 592)
 	(pt 448 608)
@@ -1646,21 +1676,6 @@ refer to the applicable agreement for further details.
 	(pt 160 256)
 	(bus)
 )
-(connector
-	(text "CLK" (rect 236 40 256 57)(font "Intel Clear" ))
-	(pt 256 56)
-	(pt 224 56)
-)
-(connector
-	(text "EXEC" (rect 386 56 411 73)(font "Intel Clear" ))
-	(pt 376 72)
-	(pt 416 72)
-)
-(connector
-	(text "FETCH" (rect 386 40 417 57)(font "Intel Clear" ))
-	(pt 376 56)
-	(pt 416 56)
-)
 (connector
 	(text "CLK" (rect 370 744 390 761)(font "Intel Clear" ))
 	(pt 360 760)
@@ -1749,109 +1764,6 @@ refer to the applicable agreement for further details.
 	(pt 912 -72)
 	(bus)
 )
-(connector
-	(pt 912 -72)
-	(pt 912 -120)
-	(bus)
-)
-(connector
-	(pt 912 -120)
-	(pt 968 -120)
-	(bus)
-)
-(connector
-	(text "COND" (rect 938 -104 967 -87)(font "Intel Clear" ))
-	(pt 968 -88)
-	(pt 928 -88)
-)
-(connector
-	(text "EXEC" (rect 938 -120 963 -103)(font "Intel Clear" ))
-	(pt 968 -104)
-	(pt 928 -104)
-)
-(connector
-	(text "R0_count" (rect 1186 -136 1230 -119)(font "Intel Clear" ))
-	(pt 1176 -120)
-	(pt 1224 -120)
-)
-(connector
-	(text "R0_en" (rect 1186 -120 1216 -103)(font "Intel Clear" ))
-	(pt 1176 -104)
-	(pt 1224 -104)
-)
-(connector
-	(text "R1_en" (rect 1186 -104 1216 -87)(font "Intel Clear" ))
-	(pt 1176 -88)
-	(pt 1224 -88)
-)
-(connector
-	(text "R2_en" (rect 1186 -88 1216 -71)(font "Intel Clear" ))
-	(pt 1176 -72)
-	(pt 1224 -72)
-)
-(connector
-	(text "R3_en" (rect 1186 -72 1216 -55)(font "Intel Clear" ))
-	(pt 1176 -56)
-	(pt 1224 -56)
-)
-(connector
-	(text "R4_en" (rect 1186 -56 1216 -39)(font "Intel Clear" ))
-	(pt 1176 -40)
-	(pt 1224 -40)
-)
-(connector
-	(text "R5_en" (rect 1186 -40 1216 -23)(font "Intel Clear" ))
-	(pt 1176 -24)
-	(pt 1224 -24)
-)
-(connector
-	(text "R6_en" (rect 1186 -24 1216 -7)(font "Intel Clear" ))
-	(pt 1176 -8)
-	(pt 1224 -8)
-)
-(connector
-	(text "R7_en" (rect 1186 -8 1216 9)(font "Intel Clear" ))
-	(pt 1176 8)
-	(pt 1224 8)
-)
-(connector
-	(text "s1[2..0]" (rect 1186 8 1220 25)(font "Intel Clear" ))
-	(pt 1176 24)
-	(pt 1224 24)
-	(bus)
-)
-(connector
-	(text "s2[2..0]" (rect 1186 24 1220 41)(font "Intel Clear" ))
-	(pt 1176 40)
-	(pt 1224 40)
-	(bus)
-)
-(connector
-	(text "s3[2..0]" (rect 1186 40 1220 57)(font "Intel Clear" ))
-	(pt 1176 56)
-	(pt 1224 56)
-	(bus)
-)
-(connector
-	(text "s4" (rect 1186 56 1196 73)(font "Intel Clear" ))
-	(pt 1176 72)
-	(pt 1224 72)
-)
-(connector
-	(text "RAMd_en" (rect 1186 88 1233 105)(font "Intel Clear" ))
-	(pt 1176 104)
-	(pt 1224 104)
-)
-(connector
-	(text "RAMi_en" (rect 1186 104 1229 121)(font "Intel Clear" ))
-	(pt 1176 120)
-	(pt 1224 120)
-)
-(connector
-	(text "RAMd_wren" (rect 1186 72 1245 89)(font "Intel Clear" ))
-	(pt 1176 88)
-	(pt 1240 88)
-)
 (connector
 	(pt 472 -112)
 	(pt 488 -112)
@@ -1875,7 +1787,7 @@ refer to the applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "s1[2..0]" (rect 462 105 479 139)(font "Intel Clear" )(vertical))
+	(text "s1[2..0]" (rect 461 104 478 138)(font "Intel Clear" )(vertical))
 	(pt 480 128)
 	(pt 480 104)
 	(bus)
@@ -1927,6 +1839,161 @@ refer to the applicable agreement for further details.
 	(pt 1024 488)
 	(pt 1048 488)
 )
+(connector
+	(text "FETCH" (rect 418 32 449 49)(font "Intel Clear" ))
+	(pt 408 48)
+	(pt 448 48)
+)
+(connector
+	(text "CLK" (rect 236 32 256 49)(font "Intel Clear" ))
+	(pt 256 48)
+	(pt 224 48)
+)
+(connector
+	(text "E2" (rect 234 48 245 65)(font "Intel Clear" ))
+	(pt 256 64)
+	(pt 224 64)
+)
+(connector
+	(text "EXEC2" (rect 418 64 449 81)(font "Intel Clear" ))
+	(pt 408 80)
+	(pt 448 80)
+)
+(connector
+	(text "EXEC1" (rect 418 48 449 65)(font "Intel Clear" ))
+	(pt 408 64)
+	(pt 448 64)
+)
+(connector
+	(text "R0_count" (rect 1186 -168 1230 -151)(font "Intel Clear" ))
+	(pt 1176 -152)
+	(pt 1224 -152)
+)
+(connector
+	(text "R0_en" (rect 1186 -152 1216 -135)(font "Intel Clear" ))
+	(pt 1176 -136)
+	(pt 1224 -136)
+)
+(connector
+	(text "R1_en" (rect 1186 -136 1216 -119)(font "Intel Clear" ))
+	(pt 1176 -120)
+	(pt 1224 -120)
+)
+(connector
+	(text "R2_en" (rect 1186 -120 1216 -103)(font "Intel Clear" ))
+	(pt 1176 -104)
+	(pt 1224 -104)
+)
+(connector
+	(text "R3_en" (rect 1186 -104 1216 -87)(font "Intel Clear" ))
+	(pt 1176 -88)
+	(pt 1224 -88)
+)
+(connector
+	(text "R4_en" (rect 1186 -88 1216 -71)(font "Intel Clear" ))
+	(pt 1176 -72)
+	(pt 1224 -72)
+)
+(connector
+	(text "R5_en" (rect 1186 -72 1216 -55)(font "Intel Clear" ))
+	(pt 1176 -56)
+	(pt 1224 -56)
+)
+(connector
+	(text "R6_en" (rect 1186 -56 1216 -39)(font "Intel Clear" ))
+	(pt 1176 -40)
+	(pt 1224 -40)
+)
+(connector
+	(text "R7_en" (rect 1186 -40 1216 -23)(font "Intel Clear" ))
+	(pt 1176 -24)
+	(pt 1224 -24)
+)
+(connector
+	(text "s1[2..0]" (rect 1186 -24 1220 -7)(font "Intel Clear" ))
+	(pt 1176 -8)
+	(pt 1224 -8)
+	(bus)
+)
+(connector
+	(text "s2[2..0]" (rect 1186 -8 1220 9)(font "Intel Clear" ))
+	(pt 1176 8)
+	(pt 1224 8)
+	(bus)
+)
+(connector
+	(text "s3[2..0]" (rect 1186 8 1220 25)(font "Intel Clear" ))
+	(pt 1176 24)
+	(pt 1224 24)
+	(bus)
+)
+(connector
+	(text "s4" (rect 1186 24 1196 41)(font "Intel Clear" ))
+	(pt 1176 40)
+	(pt 1224 40)
+)
+(connector
+	(text "RAMd_en" (rect 1186 56 1233 73)(font "Intel Clear" ))
+	(pt 1176 72)
+	(pt 1224 72)
+)
+(connector
+	(text "RAMi_en" (rect 1186 72 1229 89)(font "Intel Clear" ))
+	(pt 1176 88)
+	(pt 1224 88)
+)
+(connector
+	(text "RAMd_wren" (rect 1186 40 1245 57)(font "Intel Clear" ))
+	(pt 1176 56)
+	(pt 1240 56)
+)
+(connector
+	(text "EXEC1" (rect 938 -152 969 -135)(font "Intel Clear" ))
+	(pt 968 -136)
+	(pt 928 -136)
+)
+(connector
+	(text "COND" (rect 938 -120 967 -103)(font "Intel Clear" ))
+	(pt 928 -104)
+	(pt 968 -104)
+)
+(connector
+	(text "ALU_en" (rect 1186 88 1223 105)(font "Intel Clear" ))
+	(pt 1176 104)
+	(pt 1224 104)
+)
+(connector
+	(text "EXEC2" (rect 938 -136 969 -119)(font "Intel Clear" ))
+	(pt 968 -120)
+	(pt 928 -120)
+)
+(connector
+	(pt 968 -152)
+	(pt 912 -152)
+	(bus)
+)
+(connector
+	(text "instr[15..10]" (rect 888 -65 905 -10)(font "Intel Clear" )(vertical))
+	(pt 912 -72)
+	(pt 912 0)
+	(bus)
+)
+(connector
+	(text "instr[15..0]" (rect 888 -148 905 -99)(font "Intel Clear" )(vertical))
+	(pt 912 -152)
+	(pt 912 -72)
+	(bus)
+)
+(connector
+	(text "EXEC1" (rect 783 -28 800 3)(font "Intel Clear" )(vertical))
+	(pt 800 -32)
+	(pt 800 8)
+)
+(connector
+	(text "E2" (rect 1186 104 1197 121)(font "Intel Clear" ))
+	(pt 1176 120)
+	(pt 1224 120)
+)
 (junction (pt 504 416))
 (junction (pt 504 192))
 (junction (pt 520 432))
@@ -1959,3 +2026,4 @@ refer to the applicable agreement for further details.
 (junction (pt 160 448))
 (junction (pt 856 192))
 (junction (pt 872 -72))
+(junction (pt 912 -72))
diff --git a/CPUProject.qsf b/CPUProject.qsf
index 5c5e7ba..0ad5ce2 100644
--- a/CPUProject.qsf
+++ b/CPUProject.qsf
@@ -38,10 +38,10 @@
 
 set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE AUTO
-set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
+set_global_assignment -name TOP_LEVEL_ENTITY DECODE
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11  MAY 20, 2020"
-set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
@@ -53,13 +53,14 @@ set_global_assignment -name BDF_FILE reg_file.bdf
 set_global_assignment -name BDF_FILE mux_8x16.bdf
 set_global_assignment -name QIP_FILE ram_data.qip
 set_global_assignment -name QIP_FILE ram_instr.qip
-set_global_assignment -name BDF_FILE SM.bdf
 set_global_assignment -name VERILOG_FILE DECODE.v
 set_global_assignment -name MIF_FILE data.mif
 set_global_assignment -name MIF_FILE instr.mif
 set_global_assignment -name BDF_FILE mul16.bdf
 set_global_assignment -name QIP_FILE LUT.qip
 set_global_assignment -name VERILOG_FILE min.v
+set_global_assignment -name VERILOG_FILE SM.v
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
diff --git a/DECODE.bsf b/DECODE.bsf
index 86b527f..59e6f44 100644
--- a/DECODE.bsf
+++ b/DECODE.bsf
@@ -20,9 +20,9 @@ refer to the applicable agreement for further details.
 */
 (header "symbol" (version "1.1"))
 (symbol
-	(rect 16 16 224 320)
+	(rect 16 16 224 352)
 	(text "DECODE" (rect 5 0 47 12)(font "Arial" ))
-	(text "inst" (rect 8 288 20 300)(font "Arial" ))
+	(text "inst" (rect 8 320 20 332)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
@@ -33,17 +33,24 @@ refer to the applicable agreement for further details.
 	(port
 		(pt 0 48)
 		(input)
-		(text "EXEC" (rect 0 0 27 12)(font "Arial" ))
-		(text "EXEC" (rect 21 43 48 55)(font "Arial" ))
+		(text "EXEC1" (rect 0 0 30 12)(font "Arial" ))
+		(text "EXEC1" (rect 21 43 51 55)(font "Arial" ))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "COND_result" (rect 0 0 55 12)(font "Arial" ))
-		(text "COND_result" (rect 21 59 76 71)(font "Arial" ))
+		(text "EXEC2" (rect 0 0 31 12)(font "Arial" ))
+		(text "EXEC2" (rect 21 59 52 71)(font "Arial" ))
 		(line (pt 0 64)(pt 16 64)(line_width 1))
 	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "COND_result" (rect 0 0 55 12)(font "Arial" ))
+		(text "COND_result" (rect 21 75 76 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
 	(port
 		(pt 208 32)
 		(output)
@@ -156,7 +163,21 @@ refer to the applicable agreement for further details.
 		(text "RAMi_en" (rect 146 267 187 279)(font "Arial" ))
 		(line (pt 208 272)(pt 192 272)(line_width 1))
 	)
+	(port
+		(pt 208 288)
+		(output)
+		(text "ALU_en" (rect 0 0 36 12)(font "Arial" ))
+		(text "ALU_en" (rect 151 283 187 295)(font "Arial" ))
+		(line (pt 208 288)(pt 192 288)(line_width 1))
+	)
+	(port
+		(pt 208 304)
+		(output)
+		(text "E2" (rect 0 0 11 12)(font "Arial" ))
+		(text "E2" (rect 176 299 187 311)(font "Arial" ))
+		(line (pt 208 304)(pt 192 304)(line_width 1))
+	)
 	(drawing
-		(rectangle (rect 16 16 192 288)(line_width 1))
+		(rectangle (rect 16 16 192 320)(line_width 1))
 	)
 )
diff --git a/DECODE.v b/DECODE.v
index 343e848..c958414 100644
--- a/DECODE.v
+++ b/DECODE.v
@@ -1,7 +1,8 @@
 module DECODE
 (
 	input [15:0] instr,
-	input EXEC,
+	input EXEC1,
+	input EXEC2,
 	input COND_result,
 	output R0_count,
 	output R0_en,
@@ -18,7 +19,9 @@ module DECODE
 	output s4,
 	output RAMd_wren,
 	output RAMd_en,
-	output RAMi_en
+	output RAMi_en,
+	output ALU_en,
+	output E2
 );
 
 	wire msb = instr[15];					//MSB of the instruction word
@@ -35,54 +38,36 @@ module DECODE
 	wire STORE = msb & ls;
 	wire UJMP = ~op[5] & ~op[4] & ~op[3] & ~op[2];
 	wire JMP = (~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]);
-	wire AND = ~op[5] & ~op[4] &  op[3] &  op[2] & ~op[1] & ~op[0];
-	wire OR =  ~op[5] & ~op[4] &  op[3] &  op[2] & ~op[1] &  op[0];
-	wire XOR = ~op[5] & ~op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
-	wire NOT = ~op[5] & ~op[4] &  op[3] &  op[2] &  op[1] &  op[0];
-	wire NND = ~op[5] &  op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
-	wire NOR = ~op[5] &  op[4] & ~op[3] & ~op[2] & ~op[1] &  op[0];
-	wire XNR = ~op[5] &  op[4] & ~op[3] & ~op[2] &  op[1] & ~op[0];
-	wire MOV = ~op[5] &  op[4] & ~op[3] & ~op[2] &  op[1] &  op[0];
-	wire ADD = ~op[5] &  op[4] & ~op[3] &  op[2] & ~op[1] & ~op[0];
-	wire ADC = ~op[5] &  op[4] & ~op[3] &  op[2] & ~op[1] &  op[0];
-	wire ADO = ~op[5] &  op[4] & ~op[3] &  op[2] &  op[1] & ~op[0];
-	wire SUB = ~op[5] &  op[4] &  op[3] & ~op[2] & ~op[1] & ~op[0];
-	wire SBC = ~op[5] &  op[4] &  op[3] & ~op[2] & ~op[1] &  op[0];
-	wire SBO = ~op[5] &  op[4] &  op[3] & ~op[2] &  op[1] & ~op[0];
 	wire MUL = ~op[5] &  op[4] &  op[3] &  op[2] & ~op[1] & ~op[0];
 	wire MLA = ~op[5] &  op[4] &  op[3] &  op[2] & ~op[1] &  op[0];
 	wire MLS = ~op[5] &  op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
-	wire MRT = ~op[5] &  op[4] &  op[3] &  op[2] &  op[1] &  op[0];
-	wire LSL =  op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
-	wire LSR =  op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] &  op[0];
-	wire ASR =  op[5] & ~op[4] & ~op[3] & ~op[2] &  op[1] & ~op[0];
-	wire ROR =  op[5] & ~op[4] & ~op[3] &  op[2] & ~op[1] & ~op[0];
-	wire RRC =  op[5] & ~op[4] & ~op[3] &  op[2] & ~op[1] &  op[0];
 	wire NOP =  op[5] &  op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
 	wire STP =  op[5] &  op[4] &  op[3] &  op[2] &  op[1] &  op[0];
-
-	assign R0_count = EXEC & (~(UJMP | JMP | STP));
-	assign R0_en = EXEC & (~(STORE | NOP | STP) & ~Rd[2] & ~Rd[1] & ~Rd[0] | LOAD & ~Rls[2] & ~Rls[1] & ~Rls[0] | UJMP | JMP & COND_result);
-	assign R1_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] & ~Rd[1] &  Rd[0] | LOAD & ~Rls[2] & ~Rls[1] &  Rls[0]);
-	assign R2_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] &  Rd[1] & ~Rd[0] | LOAD & ~Rls[2] &  Rls[1] & ~Rls[0]);
-	assign R3_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] &  Rd[1] &  Rd[0] | LOAD & ~Rls[2] &  Rls[1] &  Rls[0]);
-	assign R4_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] & ~Rd[1] & ~Rd[0] | LOAD &  Rls[2] & ~Rls[1] & ~Rls[0]);
-	assign R5_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] & ~Rd[1] &  Rd[0] | LOAD &  Rls[2] & ~Rls[1] &  Rls[0]);
-	assign R6_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] &  Rd[1] & ~Rd[0] | LOAD &  Rls[2] &  Rls[1] & ~Rls[0]);
-	assign R7_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] &  Rd[1] &  Rd[0] | LOAD &  Rls[2] &  Rls[1] &  Rls[0]);
-	assign s1[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[2]) | (STORE & Rls[2]));
-	assign s1[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[1]) | (STORE & Rls[1]));
-	assign s1[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[0]) | (STORE & Rls[0]));
-	assign s2[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[2]);
-	assign s2[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[1]);
-	assign s2[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[0]);
-	assign s3[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[2]);
-	assign s3[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[1]);
-	assign s3[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[0]);
-	assign s4 = EXEC & ~(LOAD | STORE);
-	assign RAMd_wren = EXEC & STORE;
-	assign RAMd_en = EXEC & (STORE | LOAD);
-	assign RAMi_en = EXEC & ~STP;
+	
+	assign R0_count = EXEC1 & (~(UJMP | JMP | STP));
+	assign R0_en = EXEC1 & (~(STORE | NOP | STP) & ~Rd[2] & ~Rd[1] & ~Rd[0] | UJMP | JMP & COND_result) | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] & ~Rls[1] & ~Rls[0];
+	assign R1_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & ~Rd[2] & ~Rd[1] &  Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] & ~Rls[1] &  Rls[0];
+	assign R2_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & ~Rd[2] &  Rd[1] & ~Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] &  Rls[1] & ~Rls[0];
+	assign R3_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & ~Rd[2] &  Rd[1] &  Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] &  Rls[1] &  Rls[0];
+	assign R4_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) &  Rd[2] & ~Rd[1] & ~Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) &  Rls[2] & ~Rls[1] & ~Rls[0];
+	assign R5_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) &  Rd[2] & ~Rd[1] &  Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) &  Rls[2] & ~Rls[1] &  Rls[0];
+	assign R6_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) &  Rd[2] &  Rd[1] & ~Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) &  Rls[2] &  Rls[1] & ~Rls[0];
+	assign R7_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) &  Rd[2] &  Rd[1] &  Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) &  Rls[2] &  Rls[1] &  Rls[0];
+	assign s1[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[2]) | (STORE & Rls[2]));
+	assign s1[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[1]) | (STORE & Rls[1]));
+	assign s1[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[0]) | (STORE & Rls[0]));
+	assign s2[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[2]);
+	assign s2[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[1]);
+	assign s2[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[0]);
+	assign s3[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[2]);
+	assign s3[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[1]);
+	assign s3[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[0]);
+	assign s4 = EXEC1 & ~(LOAD | STORE);
+	assign RAMd_wren = EXEC1 & STORE;
+	assign RAMd_en = EXEC1 & (STORE | LOAD);
+	assign RAMi_en = EXEC1 & ~STP | EXEC2 & (LOAD | MUL | MLA | MLS);
+	assign ALU_en = LOAD | STORE;
+	assign E2 = EXEC1 & (LOAD | MUL | MLA | MLS);
 	
 endmodule
 	
\ No newline at end of file
diff --git a/DECODE.v.bak b/DECODE.v.bak
new file mode 100644
index 0000000..343e848
--- /dev/null
+++ b/DECODE.v.bak
@@ -0,0 +1,88 @@
+module DECODE
+(
+	input [15:0] instr,
+	input EXEC,
+	input COND_result,
+	output R0_count,
+	output R0_en,
+	output R1_en,
+	output R2_en,
+	output R3_en,
+	output R4_en,
+	output R5_en,
+	output R6_en,
+	output R7_en,
+	output [2:0] s1,
+	output [2:0] s2,
+	output [2:0] s3,
+	output s4,
+	output RAMd_wren,
+	output RAMd_en,
+	output RAMi_en
+);
+
+	wire msb = instr[15];					//MSB of the instruction word
+	wire ls = instr[14];						//LOAD or STORE bit
+	wire [2:0] Rls = instr[13:11];		//Register in the LOAD/STORE operation
+	wire [10:0] addr = instr[10:0];		//Memory address in the LOAD/STORE operation
+	wire [5:0] op = instr[14:9];			//Opcode in regular instructions
+	wire [2:0] Rd = instr[8:6];			//Destination register in command
+	wire [2:0] Rs1 = instr[5:3];			//Source register 1 in command
+	wire [2:0] Rs2 = instr[2:0];			//Source register 2 in command
+	
+	//Different opcodes (refer to documentation):
+	wire LOAD = msb & ~ls;
+	wire STORE = msb & ls;
+	wire UJMP = ~op[5] & ~op[4] & ~op[3] & ~op[2];
+	wire JMP = (~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]);
+	wire AND = ~op[5] & ~op[4] &  op[3] &  op[2] & ~op[1] & ~op[0];
+	wire OR =  ~op[5] & ~op[4] &  op[3] &  op[2] & ~op[1] &  op[0];
+	wire XOR = ~op[5] & ~op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
+	wire NOT = ~op[5] & ~op[4] &  op[3] &  op[2] &  op[1] &  op[0];
+	wire NND = ~op[5] &  op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
+	wire NOR = ~op[5] &  op[4] & ~op[3] & ~op[2] & ~op[1] &  op[0];
+	wire XNR = ~op[5] &  op[4] & ~op[3] & ~op[2] &  op[1] & ~op[0];
+	wire MOV = ~op[5] &  op[4] & ~op[3] & ~op[2] &  op[1] &  op[0];
+	wire ADD = ~op[5] &  op[4] & ~op[3] &  op[2] & ~op[1] & ~op[0];
+	wire ADC = ~op[5] &  op[4] & ~op[3] &  op[2] & ~op[1] &  op[0];
+	wire ADO = ~op[5] &  op[4] & ~op[3] &  op[2] &  op[1] & ~op[0];
+	wire SUB = ~op[5] &  op[4] &  op[3] & ~op[2] & ~op[1] & ~op[0];
+	wire SBC = ~op[5] &  op[4] &  op[3] & ~op[2] & ~op[1] &  op[0];
+	wire SBO = ~op[5] &  op[4] &  op[3] & ~op[2] &  op[1] & ~op[0];
+	wire MUL = ~op[5] &  op[4] &  op[3] &  op[2] & ~op[1] & ~op[0];
+	wire MLA = ~op[5] &  op[4] &  op[3] &  op[2] & ~op[1] &  op[0];
+	wire MLS = ~op[5] &  op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
+	wire MRT = ~op[5] &  op[4] &  op[3] &  op[2] &  op[1] &  op[0];
+	wire LSL =  op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
+	wire LSR =  op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] &  op[0];
+	wire ASR =  op[5] & ~op[4] & ~op[3] & ~op[2] &  op[1] & ~op[0];
+	wire ROR =  op[5] & ~op[4] & ~op[3] &  op[2] & ~op[1] & ~op[0];
+	wire RRC =  op[5] & ~op[4] & ~op[3] &  op[2] & ~op[1] &  op[0];
+	wire NOP =  op[5] &  op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
+	wire STP =  op[5] &  op[4] &  op[3] &  op[2] &  op[1] &  op[0];
+
+	assign R0_count = EXEC & (~(UJMP | JMP | STP));
+	assign R0_en = EXEC & (~(STORE | NOP | STP) & ~Rd[2] & ~Rd[1] & ~Rd[0] | LOAD & ~Rls[2] & ~Rls[1] & ~Rls[0] | UJMP | JMP & COND_result);
+	assign R1_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] & ~Rd[1] &  Rd[0] | LOAD & ~Rls[2] & ~Rls[1] &  Rls[0]);
+	assign R2_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] &  Rd[1] & ~Rd[0] | LOAD & ~Rls[2] &  Rls[1] & ~Rls[0]);
+	assign R3_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] &  Rd[1] &  Rd[0] | LOAD & ~Rls[2] &  Rls[1] &  Rls[0]);
+	assign R4_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] & ~Rd[1] & ~Rd[0] | LOAD &  Rls[2] & ~Rls[1] & ~Rls[0]);
+	assign R5_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] & ~Rd[1] &  Rd[0] | LOAD &  Rls[2] & ~Rls[1] &  Rls[0]);
+	assign R6_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] &  Rd[1] & ~Rd[0] | LOAD &  Rls[2] &  Rls[1] & ~Rls[0]);
+	assign R7_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] &  Rd[1] &  Rd[0] | LOAD &  Rls[2] &  Rls[1] &  Rls[0]);
+	assign s1[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[2]) | (STORE & Rls[2]));
+	assign s1[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[1]) | (STORE & Rls[1]));
+	assign s1[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[0]) | (STORE & Rls[0]));
+	assign s2[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[2]);
+	assign s2[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[1]);
+	assign s2[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[0]);
+	assign s3[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[2]);
+	assign s3[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[1]);
+	assign s3[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[0]);
+	assign s4 = EXEC & ~(LOAD | STORE);
+	assign RAMd_wren = EXEC & STORE;
+	assign RAMd_en = EXEC & (STORE | LOAD);
+	assign RAMi_en = EXEC & ~STP;
+	
+endmodule
+	
\ No newline at end of file
diff --git a/SM.bdf b/SM.bdf
deleted file mode 100644
index b687e5a..0000000
--- a/SM.bdf
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2018  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details.
-*/
-(header "graphic" (version "1.4"))
-(pin
-	(input)
-	(rect 272 296 440 312)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "CLK" (rect 5 0 27 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 84 12)(pt 109 12))
-		(line (pt 84 4)(pt 109 4))
-		(line (pt 113 8)(pt 168 8))
-		(line (pt 84 12)(pt 84 4))
-		(line (pt 109 4)(pt 113 8))
-		(line (pt 109 12)(pt 113 8))
-	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(output)
-	(rect 736 192 912 208)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "FETCH" (rect 90 0 126 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 736 224 912 240)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "EXEC" (rect 90 0 115 17)(font "Intel Clear" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(symbol
-	(rect 448 216 624 360)
-	(text "LPM_FF" (rect 19 0 78 16)(font "Arial" (font_size 10)))
-	(text "STATE" (rect 3 133 41 147)(font "Arial" (font_size 8)))
-	(port
-		(pt 88 144)
-		(input)
-		(text "aclr" (rect 80 113 101 127)(font "Arial" (font_size 8)))
-		(text "aclr" (rect 80 113 101 127)(font "Arial" (font_size 8)))
-		(line (pt 88 144)(pt 88 128))
-		(unused)
-	)
-	(port
-		(pt 0 24)
-		(input)
-		(text "aload" (rect 20 17 50 31)(font "Arial" (font_size 8)))
-		(text "aload" (rect 20 17 50 31)(font "Arial" (font_size 8)))
-		(line (pt 0 24)(pt 16 24))
-		(unused)
-	)
-	(port
-		(pt 88 0)
-		(input)
-		(text "aset" (rect 79 17 103 31)(font "Arial" (font_size 8)))
-		(text "aset" (rect 79 17 103 31)(font "Arial" (font_size 8)))
-		(line (pt 88 16)(pt 88 0))
-		(unused)
-	)
-	(port
-		(pt 0 88)
-		(input)
-		(text "clock" (rect 20 81 49 95)(font "Arial" (font_size 8))(invisible))
-		(text "clock" (rect 20 81 49 95)(font "Arial" (font_size 8))(invisible))
-		(line (pt 0 88)(pt 16 88))
-	)
-	(port
-		(pt 0 72)
-		(input)
-		(text "data[LPM_WIDTH-1..0]" (rect 20 63 146 77)(font "Arial" (font_size 8)))
-		(text "data[]" (rect 20 63 51 77)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 16 72)(line_width 3))
-	)
-	(port
-		(pt 0 104)
-		(input)
-		(text "enable" (rect 20 97 57 111)(font "Arial" (font_size 8)))
-		(text "enable" (rect 20 97 57 111)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 16 104))
-		(unused)
-	)
-	(port
-		(pt 0 120)
-		(input)
-		(text "sclr" (rect 20 113 41 127)(font "Arial" (font_size 8)))
-		(text "sclr" (rect 20 113 41 127)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 16 120))
-		(unused)
-	)
-	(port
-		(pt 0 56)
-		(input)
-		(text "sload" (rect 20 49 50 63)(font "Arial" (font_size 8)))
-		(text "sload" (rect 20 49 50 63)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 16 56))
-		(unused)
-	)
-	(port
-		(pt 0 40)
-		(input)
-		(text "sset" (rect 20 33 44 47)(font "Arial" (font_size 8)))
-		(text "sset" (rect 20 33 44 47)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 16 40))
-		(unused)
-	)
-	(port
-		(pt 176 88)
-		(output)
-		(text "q[LPM_WIDTH-1..0]" (rect 144 81 252 95)(font "Arial" (font_size 8)))
-		(text "q[]" (rect 144 81 158 95)(font "Arial" (font_size 8)))
-		(line (pt 160 88)(pt 176 88)(line_width 3))
-	)
-	(parameter
-		"LPM_AVALUE"
-		""
-		"Unsigned value associated with the aset port"
-	)
-	(parameter
-		"LPM_FFTYPE"
-		"\"DFF\""
-		"Selects behavior as DFF or TFF"
-		"\"DFF\"" "\"TFF\"" 
-	)
-	(parameter
-		"LPM_SVALUE"
-		""
-		"Unsigned value associated with the sset port"
-	)
-	(parameter
-		"LPM_WIDTH"
-		"1"
-		"Width of I/O, any integer > 0"
-		" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64" 
-	)
-	(drawing
-		(line (pt 16 16)(pt 160 16))
-		(line (pt 16 128)(pt 160 128))
-		(line (pt 160 128)(pt 160 16))
-		(line (pt 16 128)(pt 16 16))
-		(line (pt 16 80)(pt 24 88))
-		(line (pt 24 88)(pt 16 96))
-	)
-	(annotation_block (parameter)(rect 624 216 648 232))
-)
-(symbol
-	(rect 512 168 560 200)
-	(text "NOT" (rect 27 0 47 10)(font "Arial" (font_size 6)))
-	(text "NOT1" (rect 17 21 45 33)(font "Arial" ))
-	(port
-		(pt 48 16)
-		(input)
-		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 35 7 46 19)(font "Courier New" (bold))(invisible))
-		(line (pt 48 16)(pt 35 16))
-	)
-	(port
-		(pt 0 16)
-		(output)
-		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect -1 7 16 19)(font "Courier New" (bold))(invisible))
-		(line (pt 9 16)(pt 0 16))
-	)
-	(drawing
-		(line (pt 35 25)(pt 35 7))
-		(line (pt 35 7)(pt 17 16))
-		(line (pt 35 25)(pt 17 16))
-		(circle (rect 9 12 17 20))
-	)
-	(flipy)
-)
-(symbol
-	(rect 680 184 728 216)
-	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
-	(text "NOT2" (rect 3 21 31 33)(font "Arial" ))
-	(port
-		(pt 0 16)
-		(input)
-		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
-		(line (pt 0 16)(pt 13 16))
-	)
-	(port
-		(pt 48 16)
-		(output)
-		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
-		(line (pt 39 16)(pt 48 16))
-	)
-	(drawing
-		(line (pt 13 25)(pt 13 7))
-		(line (pt 13 7)(pt 31 16))
-		(line (pt 13 25)(pt 31 16))
-		(circle (rect 31 12 39 20))
-	)
-)
-(connector
-	(pt 448 304)
-	(pt 440 304)
-)
-(connector
-	(pt 624 304)
-	(pt 664 304)
-)
-(connector
-	(pt 560 184)
-	(pt 664 184)
-)
-(connector
-	(pt 512 184)
-	(pt 432 184)
-)
-(connector
-	(pt 432 184)
-	(pt 432 288)
-)
-(connector
-	(pt 432 288)
-	(pt 448 288)
-)
-(connector
-	(pt 680 200)
-	(pt 664 200)
-)
-(connector
-	(pt 664 184)
-	(pt 664 200)
-)
-(connector
-	(pt 728 200)
-	(pt 736 200)
-)
-(connector
-	(pt 736 232)
-	(pt 664 232)
-)
-(connector
-	(pt 664 200)
-	(pt 664 232)
-)
-(connector
-	(pt 664 232)
-	(pt 664 304)
-)
-(junction (pt 664 200))
-(junction (pt 664 232))
diff --git a/SM.bsf b/SM.bsf
index 69de486..7046e8d 100644
--- a/SM.bsf
+++ b/SM.bsf
@@ -18,33 +18,47 @@ the sole purpose of programming logic devices manufactured by
 Intel and sold by Intel or its authorized distributors.  Please
 refer to the applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 16 16 136 112)
-	(text "SM" (rect 5 0 23 19)(font "Intel Clear" (font_size 8)))
-	(text "inst" (rect 8 75 24 92)(font "Intel Clear" ))
+	(rect 16 16 168 128)
+	(text "SM" (rect 5 0 19 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
-		(text "CLK" (rect 21 27 44 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 32)(pt 16 32))
+		(text "CLK" (rect 0 0 20 12)(font "Arial" ))
+		(text "CLK" (rect 21 27 41 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
-		(pt 120 32)
-		(output)
-		(text "FETCH" (rect 0 0 40 19)(font "Intel Clear" (font_size 8)))
-		(text "FETCH" (rect 59 27 99 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 120 32)(pt 104 32))
+		(pt 0 48)
+		(input)
+		(text "E2" (rect 0 0 11 12)(font "Arial" ))
+		(text "E2" (rect 21 43 32 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
-		(pt 120 48)
+		(pt 152 32)
 		(output)
-		(text "EXEC" (rect 0 0 30 19)(font "Intel Clear" (font_size 8)))
-		(text "EXEC" (rect 69 43 99 62)(font "Intel Clear" (font_size 8)))
-		(line (pt 120 48)(pt 104 48))
+		(text "FETCH" (rect 0 0 33 12)(font "Arial" ))
+		(text "FETCH" (rect 98 27 131 39)(font "Arial" ))
+		(line (pt 152 32)(pt 136 32)(line_width 1))
+	)
+	(port
+		(pt 152 48)
+		(output)
+		(text "EXEC1" (rect 0 0 30 12)(font "Arial" ))
+		(text "EXEC1" (rect 101 43 131 55)(font "Arial" ))
+		(line (pt 152 48)(pt 136 48)(line_width 1))
+	)
+	(port
+		(pt 152 64)
+		(output)
+		(text "EXEC2" (rect 0 0 31 12)(font "Arial" ))
+		(text "EXEC2" (rect 100 59 131 71)(font "Arial" ))
+		(line (pt 152 64)(pt 136 64)(line_width 1))
 	)
 	(drawing
-		(rectangle (rect 16 16 104 80))
+		(rectangle (rect 16 16 136 96)(line_width 1))
 	)
 )
diff --git a/SM.v b/SM.v
new file mode 100644
index 0000000..b1be002
--- /dev/null
+++ b/SM.v
@@ -0,0 +1,22 @@
+module SM
+(
+	input CLK,
+	input E2,
+	output FETCH,
+	output EXEC1,
+	output EXEC2
+);
+
+reg [2:0]s = 3'b1; //current state initialised to 001
+
+always @(posedge CLK) //Change on rising edge of clock
+	begin
+	s[2] <= ~s[2] & s[1] & ~s[0] & E2;
+	s[1] <= ~s[2] & ~s[1] & s[0];
+	s[0] <= (~s[2] & s[1] & ~s[0] & ~E2) | (s[2] & ~s[1] & ~s[0]);
+	end
+
+	assign FETCH = s[0];
+	assign EXEC1 = s[1];
+	assign EXEC2 = s[2];
+endmodule
diff --git a/SM.v.bak b/SM.v.bak
new file mode 100644
index 0000000..447cb21
--- /dev/null
+++ b/SM.v.bak
@@ -0,0 +1,22 @@
+module SM
+(
+	input CLK,
+	input E2,
+	output FETCH,
+	output EXEC1,
+	output EXEC2
+);
+
+reg [2:0]s; //current state
+
+always @(posedge CLK) //Change on rising edge of clock
+	begin
+	s[2] <= ~s[2] & s[1] & ~s[0] & E2;
+	s[1] <= ~s[2] & ~s[1] & s[0];
+	s[0] <= (~s[2] & s[1] & ~s[0] & ~E2) | (s[2] & ~s[1] & ~s[0]);
+	end
+
+	assign FETCH = s[0];
+	assign EXEC1 = s[1];
+	assign EXEC2 = s[2];
+endmodule

From 3647e0b15c5a525e7a81bd58bda8ddffbc347b79 Mon Sep 17 00:00:00 2001
From: supleed2 <21363892+supleed2@users.noreply.github.com>
Date: Wed, 3 Jun 2020 15:15:44 +0100
Subject: [PATCH 3/3] ALU now uses multiply block rather than * operator

Updated to use custom block and decide which step of MUL, MLA and MLS depending on exec2 input
---
 CPUProject.qsf |  15 +++---
 CPUProject.qws | Bin 48 -> 0 bytes
 alu.v          |  70 +++++++++++-------------
 alu.v.bak      | 142 +++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 182 insertions(+), 45 deletions(-)
 delete mode 100644 CPUProject.qws
 create mode 100644 alu.v.bak

diff --git a/CPUProject.qsf b/CPUProject.qsf
index 0ad5ce2..3ca0489 100644
--- a/CPUProject.qsf
+++ b/CPUProject.qsf
@@ -38,13 +38,18 @@
 
 set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE AUTO
-set_global_assignment -name TOP_LEVEL_ENTITY DECODE
+set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11  MAY 20, 2020"
-set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name VERILOG_FILE alu.v
 set_global_assignment -name MIF_FILE LUTSquares.mif
 set_global_assignment -name BDF_FILE mul8.bdf
 set_global_assignment -name BDF_FILE abs.bdf
@@ -60,8 +65,4 @@ set_global_assignment -name BDF_FILE mul16.bdf
 set_global_assignment -name QIP_FILE LUT.qip
 set_global_assignment -name VERILOG_FILE min.v
 set_global_assignment -name VERILOG_FILE SM.v
-set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
\ No newline at end of file
diff --git a/CPUProject.qws b/CPUProject.qws
deleted file mode 100644
index 63563b76eda4b19c3f4f321afd3f1b7df67b8d5e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 48
ocmZ?JV1NM`h8%`OhGK>ihIoc@hJ1!1hHN0O04SEskP1@-0GYrBX8-^I

diff --git a/alu.v b/alu.v
index 1389477..c38f7fb 100644
--- a/alu.v
+++ b/alu.v
@@ -1,4 +1,4 @@
-module alu (enable, Rd, Rs1, Rs2, opcode, carryin, mulresult, carryout, mul1, mul2, Rout, jump);
+module alu (enable, Rd, Rs1, Rs2, opcode, carryin, mulresult, exec2, carryout, mul1, mul2, Rout, jump);
 
 input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
 input signed [15:0] Rd; // input destination register
@@ -7,6 +7,7 @@ input signed [15:0] Rs2; // input source register 2
 input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
 input carryin; // current status of carry flip-flop
 input signed [31:0] mulresult; // 32-bit result from multiplier
+input exec2; // Input from state machine to indicate when to take in result from multiplication
 
 output carryout; // resulting carry from operation, updated each cycle
 output reg signed [15:0] mul1; // first number to be multiplied
@@ -21,7 +22,6 @@ assign Rout = alusum [15:0];
 assign carryout = alusum [16];
 assign jump = (alusum[16] && ((opcode[5:2] == 4'b0000) | (opcode[5:2] == 4'b0001) | (opcode[5:2] == 4'b0010)));
 reg [15:0] mulextra;
-reg signed [31:0] mlaresult;
 
 //Jump Conditionals:
 wire JC1, JC2, JC3, JC4, JC5, JC6, JC7, JC8;
@@ -73,23 +73,41 @@ always @(*)
 				
 				6'b011100: // MUL Multiply (Rd = Rs1 * Rs2)
 					begin
-//						mul1 = Rs1;
-//						mul2 = Rs2;
-						alusum[16] = 1'b0;
-						{mulextra, alusum[15:0]} = Rs1 * Rs2;
+						if(!exec2)
+							begin
+								mul1 = Rs1;
+								mul2 = Rs2;
+							end
+						else
+							begin
+								alusum[16] = 1'b0;
+								{mulextra, alusum[15:0]} = mulresult;
+							end
 					end
 				6'b011101: // MLA Multiply and Add  (Rd = Rs2 + (Rd * Rs1))
 					begin
-//						mul1 = Rs1;
-//						mul2 = Rs2;
-						alusum[16] = 1'b0;
-						{mulextra, alusum[15:0]} = (Rd * Rs1) + Rs2;
+						if(!exec2)
+							begin
+								mul1 = Rs1;
+								mul2 = Rs2;
+							end
+						else
+							begin
+								alusum[16] = 1'b0;
+								{mulextra, alusum[15:0]} = mulresult + {16'h0000, Rs2};
+							end
 					end
 				6'b011110: // MLS Multiply and Subtract (Rd = Rs2 - (Rd * Rs1)[15:0])
 					begin
-//						mul1 = Rs1;
-//						mul2 = Rs2;
-						alusum = {1'b0, Rs2 - (Rd * Rs1)};
+						if(!exec2)
+							begin
+								mul1 = Rs1;
+								mul2 = Rs2;
+							end
+						else
+							begin
+								alusum = {1'b0, Rs2 - mulresult[15:0]};
+							end
 					end
 				6'b011111: alusum = mulextra; // MRT Retrieve Multiply MSBs (Rd = MSBs)
 				
@@ -104,7 +122,7 @@ always @(*)
 				6'b100111: ;
 				
 				6'b111110: ; // NOP No Operation (Do Nothing for a cycle)
-				6'b111111: ; // STP Stop (Program Ends)
+				6'b111111: alusum = {1'b0, 16'h0000}; // STP Stop (Program Ends)
 				
 				default: ; // During Load & Store as well as undefined opcodes
 			endcase;
@@ -115,28 +133,4 @@ always @(*)
 			end
 	end
 
-/*	
-always @(*)
-	begin
-		case (opcode)
-			6'b011100:
-				begin
-					alusum = {1'b0, mulresult[15:0]};
-					mulextra = mulresult[31:16];
-				end
-			6'b011101:
-				begin
-					mlaresult = mulresult + {16'h0000, Rs2};
-					alusum = {1'b0, mlaresult[15:0]};
-					mulextra = mlaresult[31:16];
-				end
-			6'b011110:
-				begin
-					alusum = {1'b0, Rs2 - mulresult[15:0]};
-				end
-			default: ;
-		endcase
-	end
-*/
-
 endmodule
\ No newline at end of file
diff --git a/alu.v.bak b/alu.v.bak
new file mode 100644
index 0000000..27546b7
--- /dev/null
+++ b/alu.v.bak
@@ -0,0 +1,142 @@
+module alu (enable, Rd, Rs1, Rs2, opcode, carryin, mulresult, carryout, mul1, mul2, Rout, jump);
+
+input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
+input signed [15:0] Rd; // input destination register
+input signed [15:0] Rs1; // input source register 1
+input signed [15:0] Rs2; // input source register 2
+input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
+input carryin; // current status of carry flip-flop
+input signed [31:0] mulresult; // 32-bit result from multiplier
+
+output carryout; // resulting carry from operation, updated each cycle
+output reg signed [15:0] mul1; // first number to be multiplied
+output reg signed [15:0] mul2; // second number to be multiplied
+output signed [15:0] Rout; // value to be saved to destination register
+output jump; // tells decoder whether Jump condition is true
+
+// load and store are handled outside the ALU so those opcodes can be ignored. All other instructions have a consistent format.
+
+reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
+assign Rout = alusum [15:0];
+assign carryout = alusum [16];
+assign jump = (alusum[16] && ((opcode[5:2] == 4'b0000) | (opcode[5:2] == 4'b0001) | (opcode[5:2] == 4'b0010)));
+reg [15:0] mulextra;
+reg signed [31:0] mlaresult;
+
+//Jump Conditionals:
+wire JC1, JC2, JC3, JC4, JC5, JC6, JC7, JC8;
+assign JC1 = (Rs1 < Rs2);
+assign JC2 = (Rs1 > Rs2);
+assign JC3 = (Rs1 == Rs2);
+assign JC4 = (Rs1 == 0);
+assign JC5 = (Rs1 >= Rs2);
+assign JC6 = (Rs1 <= Rs2);
+assign JC7 = (Rs1 != Rs2);
+assign JC8 = (Rs1 < 0);
+
+always @(*)
+	begin
+		if(!enable)
+			begin
+			case (opcode)
+				6'b000000: alusum = {1'b1, Rd}; // JMP Unconditional Jump, first bit high to indicate jump and passes through Rd
+				
+				6'b000100: alusum = {JC1, Rd}; // JC1 Conditional Jump A < B
+				6'b000101: alusum = {JC2, Rd}; // JC2 Conditional Jump A > B
+				6'b000110: alusum = {JC3, Rd}; // JC3 Conditional Jump A = B
+				6'b000111: alusum = {JC4, Rd}; // JC4 Conditional Jump A = 0
+				
+				6'b001000: alusum = {JC5, Rd}; // JC5 Conditional Jump A >= B / A !< B
+				6'b001001: alusum = {JC6, Rd}; // JC6 Conditional Jump A <= B / A !> B
+				6'b001010: alusum = {JC7, Rd}; // JC7 Conditional Jump A != B
+				6'b001011: alusum = {JC8, Rd}; // JC8 Conditional Jump A < 0
+				
+				6'b001100: alusum = {1'b0, Rs1 & Rs2}; // AND Bitwise AND
+				6'b001101: alusum = {1'b0, Rs1 | Rs2}; // OR Bitwise OR
+				6'b001110: alusum = {1'b0, Rs1 ^ Rs2}; // XOR Bitwise XOR
+				6'b001111: alusum = {1'b0, ~Rs1}; // NOT Bitwise NOT
+				
+				6'b010000: alusum = {1'b0, ~Rs1 | ~Rs2}; // NND Bitwise NAND
+				6'b010001: alusum = {1'b0, ~Rs1 & ~Rs2}; // NOR Bitwise NOR
+				6'b010010: alusum = {1'b0, Rs1 ~^ Rs2}; // XNR Bitwise XNOR
+				6'b010011: alusum = {1'b0, Rs1}; // MOV Move (Rd = Rs1)
+				
+				6'b010100: alusum = {1'b0, Rs1} + {1'b0, Rs2}; // ADD Add (Rd = Rs1 + Rs2)
+				6'b010101: alusum = {1'b0, Rs1} + {1'b0, Rs2} + carryin; // ADC Add w/ Carry (Rd = Rs1 + Rs2 + C)
+				6'b010110: alusum = {1'b0, Rs1} + {17'b00000000000000001}; // ADO Add 1 (Rd = Rd + 1)
+				6'b010111: ;
+				
+				6'b011000: alusum = {1'b0, Rs1} - {1'b0, Rs2}; // SUB Subtract (Rd = Rs1 - Rs2)
+				6'b011001: alusum = {1'b0, Rs1} - {1'b0, Rs2} + carryin - {17'b00000000000000001}; // SBC Subtract w/ Carry (Rd = Rs1 - Rs2 + C - 1)
+				6'b011010: alusum = {1'b0, Rs1} - {17'b00000000000000001}; // SBO Subtract 1 (Rd = Rd - 1)
+				6'b011011: ;
+				
+				6'b011100: // MUL Multiply (Rd = Rs1 * Rs2)
+					begin
+//						mul1 = Rs1;
+//						mul2 = Rs2;
+						alusum[16] = 1'b0;
+						{mulextra, alusum[15:0]} = Rs1 * Rs2;
+					end
+				6'b011101: // MLA Multiply and Add  (Rd = Rs2 + (Rd * Rs1))
+					begin
+//						mul1 = Rs1;
+//						mul2 = Rs2;
+						alusum[16] = 1'b0;
+						{mulextra, alusum[15:0]} = (Rd * Rs1) + Rs2;
+					end
+				6'b011110: // MLS Multiply and Subtract (Rd = Rs2 - (Rd * Rs1)[15:0])
+					begin
+//						mul1 = Rs1;
+//						mul2 = Rs2;
+						alusum = {1'b0, Rs2 - (Rd * Rs1)};
+					end
+				6'b011111: alusum = mulextra; // MRT Retrieve Multiply MSBs (Rd = MSBs)
+				
+				6'b100000: alusum = {1'b0, Rs1 << Rs2}; // LSL Logical Shift Left (Rd = Rs1 shifted left by value of Rs2)
+				6'b100001: alusum = {1'b0, Rs1 >> Rs2}; // LSR Logical Shift Right (Rd = Rs1 shifted right by value of Rs2)
+				6'b100010: alusum = {Rs1[15], Rs1 >>> Rs2}; // ASR Arithmetic Shift Right (Rd = Rs1 shifted right by value of Rs2, maintaining sign bit)
+				6'b100011: ;
+				
+				6'b100100: alusum = {1'b0, (Rs1 >> Rs2[3:0]) | (Rs1 << (16 - Rs2[3:0]))}; // ROR Shift Right Loop (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Rs1[15])
+				6'b100101: alusum = ({Rs1, carryin} >> (Rs2 % 17)) | ({Rs1, carryin} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
+				6'b100110: ;
+				6'b100111: ;
+				
+				6'b111110: ; // NOP No Operation (Do Nothing for a cycle)
+				6'b111111: ; // STP Stop (Program Ends)
+				
+				default: ; // During Load & Store as well as undefined opcodes
+			endcase;
+			end
+		else
+			begin
+				alusum = {1'b0, 16'h0000}; // Bring output low during Load/Store so it does not interfere
+			end
+	end
+
+/*	
+always @(*)
+	begin
+		case (opcode)
+			6'b011100:
+				begin
+					alusum = {1'b0, mulresult[15:0]};
+					mulextra = mulresult[31:16];
+				end
+			6'b011101:
+				begin
+					mlaresult = mulresult + {16'h0000, Rs2};
+					alusum = {1'b0, mlaresult[15:0]};
+					mulextra = mlaresult[31:16];
+				end
+			6'b011110:
+				begin
+					alusum = {1'b0, Rs2 - mulresult[15:0]};
+				end
+			default: ;
+		endcase
+	end
+*/
+
+endmodule
\ No newline at end of file