diff --git a/ALU_top.bdf b/ALU_top.bdf index 0a5ed61..3c8d8f0 100644 --- a/ALU_top.bdf +++ b/ALU_top.bdf @@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 2019 Intel Corporation. All rights reserved. +Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic +and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject @@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. +refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin @@ -148,22 +147,6 @@ https://fpgasoftware.intel.com/eula. ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) -(pin - (input) - (rect 344 368 528 384) - (text "INPUT" (rect 141 0 169 10)(font "Arial" (font_size 6))) - (text "memdatain[15..0]" (rect 5 0 89 17)(font "Intel Clear" )) - (pt 184 8) - (drawing - (line (pt 100 12)(pt 125 12)) - (line (pt 100 4)(pt 125 4)) - (line (pt 129 8)(pt 184 8)) - (line (pt 100 12)(pt 100 4)) - (line (pt 125 4)(pt 129 8)) - (line (pt 125 12)(pt 129 8)) - ) - (text "VCC" (rect 144 7 164 17)(font "Arial" (font_size 6))) -) (pin (output) (rect 800 272 976 288) @@ -329,9 +312,9 @@ https://fpgasoftware.intel.com/eula. ) ) (symbol - (rect 544 216 776 424) + (rect 552 216 776 392) (text "alu" (rect 5 0 19 12)(font "Arial" )) - (text "ALU_in" (rect 8 192 43 204)(font "Arial" )) + (text "ALU_in" (rect 8 160 43 172)(font "Arial" )) (port (pt 0 32) (input) @@ -363,8 +346,8 @@ https://fpgasoftware.intel.com/eula. (port (pt 0 96) (input) - (text "opcode[5..0]" (rect 0 0 61 12)(font "Arial" )) - (text "opcode[5..0]" (rect 21 91 82 103)(font "Arial" )) + (text "instr[15..0]" (rect 0 0 53 12)(font "Arial" )) + (text "instr[15..0]" (rect 21 91 74 103)(font "Arial" )) (line (pt 0 96)(pt 16 96)(line_width 3)) ) (port @@ -389,98 +372,58 @@ https://fpgasoftware.intel.com/eula. (line (pt 0 144)(pt 16 144)(line_width 3)) ) (port - (pt 0 160) - (input) - (text "memdatain[15..0]" (rect 0 0 86 12)(font "Arial" )) - (text "memdatain[15..0]" (rect 21 155 107 167)(font "Arial" )) - (line (pt 0 160)(pt 16 160)(line_width 3)) - ) - (port - (pt 232 32) + (pt 224 32) (output) (text "mul1[15..0]" (rect 0 0 55 12)(font "Arial" )) - (text "mul1[15..0]" (rect 165 27 211 39)(font "Arial" )) - (line (pt 232 32)(pt 216 32)(line_width 3)) + (text "mul1[15..0]" (rect 157 27 203 39)(font "Arial" )) + (line (pt 224 32)(pt 208 32)(line_width 3)) ) (port - (pt 232 48) + (pt 224 48) (output) (text "mul2[15..0]" (rect 0 0 55 12)(font "Arial" )) - (text "mul2[15..0]" (rect 165 43 211 55)(font "Arial" )) - (line (pt 232 48)(pt 216 48)(line_width 3)) + (text "mul2[15..0]" (rect 157 43 203 55)(font "Arial" )) + (line (pt 224 48)(pt 208 48)(line_width 3)) ) (port - (pt 232 64) + (pt 224 64) (output) (text "Rout[15..0]" (rect 0 0 55 12)(font "Arial" )) - (text "Rout[15..0]" (rect 165 59 211 71)(font "Arial" )) - (line (pt 232 64)(pt 216 64)(line_width 3)) + (text "Rout[15..0]" (rect 157 59 203 71)(font "Arial" )) + (line (pt 224 64)(pt 208 64)(line_width 3)) ) (port - (pt 232 80) + (pt 224 80) (output) (text "jump" (rect 0 0 23 12)(font "Arial" )) - (text "jump" (rect 192 75 211 87)(font "Arial" )) - (line (pt 232 80)(pt 216 80)) + (text "jump" (rect 184 75 203 87)(font "Arial" )) + (line (pt 224 80)(pt 208 80)) ) (port - (pt 232 96) + (pt 224 96) (output) (text "carry" (rect 0 0 25 12)(font "Arial" )) - (text "carry" (rect 190 91 211 103)(font "Arial" )) - (line (pt 232 96)(pt 216 96)) + (text "carry" (rect 182 91 203 103)(font "Arial" )) + (line (pt 224 96)(pt 208 96)) ) (port - (pt 232 112) + (pt 224 112) (output) (text "jumpflags[7..0]" (rect 0 0 74 12)(font "Arial" )) - (text "jumpflags[7..0]" (rect 149 107 211 119)(font "Arial" )) - (line (pt 232 112)(pt 216 112)(line_width 3)) + (text "jumpflags[7..0]" (rect 141 107 203 119)(font "Arial" )) + (line (pt 224 112)(pt 208 112)(line_width 3)) ) (port - (pt 232 128) + (pt 224 128) (output) (text "memaddr[10..0]" (rect 0 0 77 12)(font "Arial" )) - (text "memaddr[10..0]" (rect 146 123 211 135)(font "Arial" )) - (line (pt 232 128)(pt 216 128)(line_width 3)) + (text "memaddr[10..0]" (rect 138 123 203 135)(font "Arial" )) + (line (pt 224 128)(pt 208 128)(line_width 3)) ) (drawing - (rectangle (rect 16 16 216 192)) + (rectangle (rect 16 16 208 160)) ) ) -(connector - (pt 528 248) - (pt 544 248) -) -(connector - (pt 528 264) - (pt 544 264) - (bus) -) -(connector - (pt 528 280) - (pt 544 280) - (bus) -) -(connector - (pt 528 296) - (pt 544 296) - (bus) -) -(connector - (pt 528 312) - (pt 544 312) - (bus) -) -(connector - (pt 528 344) - (pt 544 344) -) -(connector - (pt 528 360) - (pt 544 360) - (bus) -) (connector (pt 752 432) (pt 752 488) @@ -520,16 +463,6 @@ https://fpgasoftware.intel.com/eula. (pt 784 440) (bus) ) -(connector - (pt 536 328) - (pt 536 432) - (bus) -) -(connector - (pt 544 328) - (pt 536 328) - (bus) -) (connector (pt 744 488) (pt 752 488) @@ -599,8 +532,46 @@ https://fpgasoftware.intel.com/eula. (bus) ) (connector - (pt 544 376) - (pt 528 376) + (pt 536 432) + (pt 536 328) + (bus) +) +(connector + (pt 528 248) + (pt 552 248) +) +(connector + (pt 528 264) + (pt 552 264) + (bus) +) +(connector + (pt 528 280) + (pt 552 280) + (bus) +) +(connector + (pt 528 296) + (pt 552 296) + (bus) +) +(connector + (pt 528 312) + (pt 552 312) + (bus) +) +(connector + (pt 536 328) + (pt 552 328) + (bus) +) +(connector + (pt 528 344) + (pt 552 344) +) +(connector + (pt 528 360) + (pt 552 360) (bus) ) (junction (pt 752 488)) diff --git a/CPUProject.qsf b/CPUProject.qsf index f6d4eb8..1e223f9 100644 --- a/CPUProject.qsf +++ b/CPUProject.qsf @@ -41,7 +41,7 @@ set_global_assignment -name DEVICE AUTO set_global_assignment -name TOP_LEVEL_ENTITY CPUProject set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020" -set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL diff --git a/DECODE.bsf b/DECODE.bsf index 8255261..7a4bebf 100644 --- a/DECODE.bsf +++ b/DECODE.bsf @@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 2019 Intel Corporation. All rights reserved. +Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic +and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject @@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. +refer to the applicable agreement for further details. */ (header "symbol" (version "1.1")) (symbol diff --git a/DECODE.v b/DECODE.v index 83f16e7..e20de6e 100644 --- a/DECODE.v +++ b/DECODE.v @@ -41,7 +41,8 @@ module DECODE //Different opcodes (refer to documentation): wire LDA = msb & ~ls; wire STA = msb & ls; - wire JMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2]; + wire JMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0]; + wire JMA = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & op[0]; wire JCX = ~msb & ((~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2])); wire MUL = ~msb & ~op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0]; wire MLA = ~msb & ~op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0]; @@ -50,37 +51,38 @@ module DECODE wire POP = ~msb & op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & op[0]; wire LDR = ~msb & op[5] & ~op[4] & op[3] & ~op[2] & op[1] & ~op[0]; wire STR = ~msb & op[5] & ~op[4] & op[3] & ~op[2] & op[1] & op[0]; + wire CLL = ~msb & op[5] & ~op[4] & ~op[3] & op[2] & op[1] & ~op[0]; + wire RTN = ~msb & op[5] & ~op[4] & ~op[3] & op[2] & op[1] & op[0]; wire NOP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0]; wire STP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & op[0]; - assign R0_count = EXEC1 & (~(JMP | (JCX & COND_result) | STP)); - assign R0_en = (EXEC1 & (~(STA | NOP | STP | LDA | PSH | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0] | JMP | JCX & COND_result)) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0]); - assign R1_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & Rd[0]); - assign R2_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & Rd[1] & ~Rd[0]); - assign R3_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & Rd[1] & Rd[0]); - assign R4_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & ~Rd[1] & ~Rd[0]); - assign R5_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & ~Rd[1] & Rd[0]); - assign R6_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & Rd[1] & ~Rd[0]); - assign R7_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & Rd[1] & Rd[0]); - assign s1[2] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[2]) | (STA & Rls[2]); - assign s1[1] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[1]) | (STA & Rls[1]); - assign s1[0] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[0]) | (STA & Rls[0]); - assign s2[2] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[2]); - assign s2[1] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[1]); - assign s2[0] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[0]); - assign s3[2] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[2]); - assign s3[1] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[1]); - assign s3[0] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[0]); + assign R0_count = EXEC1 & (~(JMP | JMA | (JCX & COND_result) | STP | CLL | RTN)); + assign R0_en = (EXEC1 & (~(STA | NOP | STP | LDA | PSH | LDR | CLL | RTN) & ~Rd[2] & ~Rd[1] & ~Rd[0] | JMP | (JCX & COND_result) | JMA)) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & RTN) | (EXEC1 & CLL); + assign R1_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & ~Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & ~Rd[2] & ~Rd[1] & Rd[0]); + assign R2_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & ~Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & ~Rd[2] & Rd[1] & ~Rd[0]); + assign R3_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & ~Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & ~Rd[2] & Rd[1] & Rd[0]); + assign R4_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & Rd[2] & ~Rd[1] & ~Rd[0]); + assign R5_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & Rd[2] & ~Rd[1] & Rd[0]); + assign R6_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & Rd[2] & Rd[1] & ~Rd[0]); + assign R7_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & Rd[2] & Rd[1] & Rd[0]); + assign s1[2] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | CLL | RTN) & Rs1[2]) | (STA & Rls[2]); + assign s1[1] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | CLL | RTN) & Rs1[1]) | (STA & Rls[1]); + assign s1[0] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | CLL | RTN) & Rs1[0]) | (STA & Rls[0]); + assign s2[2] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | PSH | LDR | STR | CLL | RTN) & Rs2[2]); + assign s2[1] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | PSH | LDR | STR | CLL | RTN) & Rs2[1]); + assign s2[0] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | PSH | LDR | STR | CLL | RTN) & Rs2[0]); + assign s3[2] = (~(STA | LDA | NOP | STP | PSH | POP | RTN) & Rd[2]); + assign s3[1] = (~(STA | LDA | NOP | STP | PSH | POP | RTN) & Rd[1]); + assign s3[0] = (~(STA | LDA | NOP | STP | PSH | POP | RTN) & Rd[0]); assign s4 = ~(LDA | LDR); assign RAMd_wren = EXEC1 & (STA | STR); assign RAMd_en = EXEC1 & (STA | LDA | STR | LDR); assign RAMi_en = FETCH; assign ALU_en = LDA | STA; - assign E2 = EXEC1 & (LDA | MUL | MLA | MLS | POP | LDR); - assign stack_en = (EXEC1 & PSH) | ((EXEC1 | EXEC2) & POP); + assign E2 = EXEC1 & (LDA | MUL | MLA | MLS | POP | LDR | RTN); + assign stack_en = (EXEC1 & (PSH | CLL | RTN | POP)); assign stack_rst = STP; - assign stack_rw = EXEC1 & PSH; + assign stack_rw = EXEC1 & (PSH | CLL); assign s5 = EXEC1 & (STR | LDR); endmodule - \ No newline at end of file diff --git a/alu.bsf b/alu.bsf index 169c1a7..dc87f3a 100644 --- a/alu.bsf +++ b/alu.bsf @@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 2019 Intel Corporation. All rights reserved. +Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic +and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject @@ -16,14 +16,13 @@ the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. +refer to the applicable agreement for further details. */ (header "symbol" (version "1.1")) (symbol - (rect 16 16 248 224) + (rect 16 16 240 192) (text "alu" (rect 5 0 15 12)(font "Arial" )) - (text "inst" (rect 8 192 20 204)(font "Arial" )) + (text "inst" (rect 8 160 20 172)(font "Arial" )) (port (pt 0 32) (input) @@ -55,8 +54,8 @@ https://fpgasoftware.intel.com/eula. (port (pt 0 96) (input) - (text "opcode[5..0]" (rect 0 0 48 12)(font "Arial" )) - (text "opcode[5..0]" (rect 21 91 69 103)(font "Arial" )) + (text "instr[15..0]" (rect 0 0 40 12)(font "Arial" )) + (text "instr[15..0]" (rect 21 91 61 103)(font "Arial" )) (line (pt 0 96)(pt 16 96)(line_width 3)) ) (port @@ -81,62 +80,55 @@ https://fpgasoftware.intel.com/eula. (line (pt 0 144)(pt 16 144)(line_width 3)) ) (port - (pt 0 160) - (input) - (text "memdatain[15..0]" (rect 0 0 67 12)(font "Arial" )) - (text "memdatain[15..0]" (rect 21 155 88 167)(font "Arial" )) - (line (pt 0 160)(pt 16 160)(line_width 3)) - ) - (port - (pt 232 32) + (pt 224 32) (output) (text "mul1[15..0]" (rect 0 0 41 12)(font "Arial" )) - (text "mul1[15..0]" (rect 170 27 211 39)(font "Arial" )) - (line (pt 232 32)(pt 216 32)(line_width 3)) + (text "mul1[15..0]" (rect 162 27 203 39)(font "Arial" )) + (line (pt 224 32)(pt 208 32)(line_width 3)) ) (port - (pt 232 48) + (pt 224 48) (output) (text "mul2[15..0]" (rect 0 0 42 12)(font "Arial" )) - (text "mul2[15..0]" (rect 169 43 211 55)(font "Arial" )) - (line (pt 232 48)(pt 216 48)(line_width 3)) + (text "mul2[15..0]" (rect 161 43 203 55)(font "Arial" )) + (line (pt 224 48)(pt 208 48)(line_width 3)) ) (port - (pt 232 64) + (pt 224 64) (output) (text "Rout[15..0]" (rect 0 0 43 12)(font "Arial" )) - (text "Rout[15..0]" (rect 168 59 211 71)(font "Arial" )) - (line (pt 232 64)(pt 216 64)(line_width 3)) + (text "Rout[15..0]" (rect 160 59 203 71)(font "Arial" )) + (line (pt 224 64)(pt 208 64)(line_width 3)) ) (port - (pt 232 80) + (pt 224 80) (output) (text "jump" (rect 0 0 18 12)(font "Arial" )) - (text "jump" (rect 193 75 211 87)(font "Arial" )) - (line (pt 232 80)(pt 216 80)(line_width 1)) + (text "jump" (rect 185 75 203 87)(font "Arial" )) + (line (pt 224 80)(pt 208 80)(line_width 1)) ) (port - (pt 232 96) + (pt 224 96) (output) (text "carry" (rect 0 0 22 12)(font "Arial" )) - (text "carry" (rect 189 91 211 103)(font "Arial" )) - (line (pt 232 96)(pt 216 96)(line_width 1)) + (text "carry" (rect 181 91 203 103)(font "Arial" )) + (line (pt 224 96)(pt 208 96)(line_width 1)) ) (port - (pt 232 112) + (pt 224 112) (output) (text "jumpflags[7..0]" (rect 0 0 57 12)(font "Arial" )) - (text "jumpflags[7..0]" (rect 154 107 211 119)(font "Arial" )) - (line (pt 232 112)(pt 216 112)(line_width 3)) + (text "jumpflags[7..0]" (rect 146 107 203 119)(font "Arial" )) + (line (pt 224 112)(pt 208 112)(line_width 3)) ) (port - (pt 232 128) + (pt 224 128) (output) (text "memaddr[10..0]" (rect 0 0 62 12)(font "Arial" )) - (text "memaddr[10..0]" (rect 149 123 211 135)(font "Arial" )) - (line (pt 232 128)(pt 216 128)(line_width 3)) + (text "memaddr[10..0]" (rect 141 123 203 135)(font "Arial" )) + (line (pt 224 128)(pt 208 128)(line_width 3)) ) (drawing - (rectangle (rect 16 16 216 192)(line_width 1)) + (rectangle (rect 16 16 208 160)(line_width 1)) ) ) diff --git a/alu.v b/alu.v index 85c49f1..731a1c6 100644 --- a/alu.v +++ b/alu.v @@ -1,14 +1,13 @@ -module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, memdatain, mul1, mul2, Rout, jump, carry, jumpflags, memaddr); +module alu (enable, Rs1, Rs2, Rd, instr, mulresult, exec2, stackout, mul1, mul2, Rout, jump, carry, jumpflags, memaddr); input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur input signed [15:0] Rs1; // input source register 1 input signed [15:0] Rs2; // input source register 2 input signed [15:0] Rd; // input destination register -input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU +input [15:0] instr; // opcode is fed in from instruction using wires outside ALU input signed [31:0] mulresult; // 32-bit result from multiplier input exec2; // Input from state machine to indicate when to take in result from multiplication input [15:0] stackout; // input from stack to be fed back to registers -input signed [15:0] memdatain; // input data from RAMd output reg signed [15:0] mul1; // first number to be multiplied output reg signed [15:0] mul2; // second number to be multiplied @@ -18,6 +17,7 @@ output reg carry; // Internal carry register that is updated during appropriate output [7:0] jumpflags; output reg [10:0] memaddr; // address to load data from / store data to RAMd +wire [5:0]opcode = instr[14:9]; //opcode of current instruction reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply assign Rout = alusum [15:0]; assign jump = (alusum[16] && ((opcode[5:2] == 4'b0000) | (opcode[5:2] == 4'b0001) | (opcode[5:2] == 4'b0010))); @@ -160,9 +160,13 @@ always @(opcode, mulresult) 6'b100011: ; 6'b100100: alusum = {1'b0, (Rs1 >> Rs2[3:0]) | (Rs1 << (16 - Rs2[3:0]))}; // ROR Shift Right Loop (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Rs1[15]) - 6'b100101: alusum = ({Rs1, carry} >> (Rs2 % 17)) | ({Rs1, carry} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15]) - 6'b100110: ; - 6'b100111: ; +// 6'b100101: alusum = ({Rs1, carry} >> (Rs2 % 17)) | ({Rs1, carry} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15]) + 6'b100110: alusum = {1'b1, Rd}; //CLL function call + 6'b100111: begin //RTN return to prev call + if(exec2) begin + alusum = {1'b0, stackout}; + end + end 6'b101000: alusum = {1'b0, Rs1}; // PSH Push value to stack (Stack = Rs1) 6'b101001: alusum = {1'b0, stackout}; // POP Pop value from stack (Rd = Stack) @@ -170,9 +174,6 @@ always @(opcode, mulresult) if(!exec2) begin memaddr = Rs1[10:0]; end - else begin - alusum = {1'b0, memdatain}; - end end 6'b101011: begin // STR Indirect Store (Mem[Rd] = Rs1) memaddr = Rd[10:0]; @@ -189,4 +190,4 @@ always @(opcode, mulresult) end end -endmodule \ No newline at end of file +endmodule