Fixed multiplier bug

This commit is contained in:
Benjamin 2020-06-13 01:41:24 +01:00
parent 87f3d0e919
commit aff07036e0
10 changed files with 364 additions and 1197 deletions

769
abs.bdf
View file

@ -1,769 +0,0 @@
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WARNING: Do NOT edit the input and output ports in this file in a text
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/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
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44
abs.bsf
View file

@ -1,44 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
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)
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View file

@ -21,38 +21,38 @@ https://fpgasoftware.intel.com/eula.
*/
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11
max_min.v Normal file
View file

@ -0,0 +1,11 @@
module max_min(a, b, maximum, minimum);
input unsigned [7:0] a;
input unsigned [7:0] b;
output unsigned [7:0] maximum;
output unsigned [7:0] minimum;
assign minimum = (a<b) ? a:b;
assign maximum = (a>b) ? a:b;
endmodule

11
max_min.v.bak Normal file
View file

@ -0,0 +1,11 @@
module min_max(a, b, minimum, maximum);
input unsigned [7..0] a;
input unsigned [7..0] b;
output unsigned [7..0] minimum;
output unsigned [7..0] maximum;
assign minimum = (a<b) ? a:b;
assign maximum = (a>b) ? a:b;
endmodule

7
min.v
View file

@ -1,7 +0,0 @@
module min(sign, a, b, num);
input sign;
input [7:0] a;
input [7:0] b;
output [7:0] num;
assign num = sign ? a[7:0]:b[7:0];
endmodule

View file

@ -1,12 +0,0 @@
module MIN(
input sign,
input a[7..0],
input b[7..0],
output [7..0] num;
);
assign num = sign ? a[7..0]:b[7..0]
endmodule

354
mul16.bdf
View file

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299
mul8.bdf
View file

@ -20,38 +20,6 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
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@ -68,6 +36,38 @@ https://fpgasoftware.intel.com/eula.
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View file

@ -21,7 +21,7 @@ https://fpgasoftware.intel.com/eula.
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