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Complete CPU v2 (not tested)
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Kacper
parent
685f69a7cf
commit
9a1a1da664
1127
CPUProject.bdf
1127
CPUProject.bdf
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@ -38,7 +38,7 @@
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE AUTO
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set_global_assignment -name TOP_LEVEL_ENTITY mux_8x16
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set_global_assignment -name TOP_LEVEL_ENTITY test
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
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@ -62,8 +62,9 @@ set_global_assignment -name VERILOG_FILE min.v
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set_global_assignment -name VERILOG_FILE SM.v
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set_global_assignment -name BDF_FILE ALU_top.bdf
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set_global_assignment -name VERILOG_FILE mux_8x16.v
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set_global_assignment -name VERILOG_FILE mux_3x16.v
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set_global_assignment -name BDF_FILE test.bdf
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VERILOG_FILE mux_3x16.v
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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27
DECODE.bsf
27
DECODE.bsf
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@ -20,9 +20,9 @@ refer to the applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 224 352)
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(rect 16 16 224 416)
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(text "DECODE" (rect 5 0 47 12)(font "Arial" ))
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(text "inst" (rect 8 384 20 396)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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@ -177,7 +177,28 @@ refer to the applicable agreement for further details.
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18
DECODE.v
18
DECODE.v
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@ -58,15 +58,15 @@ module DECODE
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assign R5_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & ~Rd[1] & Rd[0] | EXEC2 & LOAD & Rls[2] & ~Rls[1] & Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & Rd[0];
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assign R6_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & Rd[1] & ~Rd[0] | EXEC2 & LOAD & Rls[2] & Rls[1] & ~Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & ~Rd[0];
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assign R7_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & Rd[1] & Rd[0] | EXEC2 & LOAD & Rls[2] & Rls[1] & Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & Rd[0];
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assign s1[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[2]) | (STORE & Rls[2]) | (PSH & Rs1[2]));
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assign s1[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[1]) | (STORE & Rls[1]) | (PSH & Rs1[1]));
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assign s1[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[0]) | (STORE & Rls[0]) | (PSH & Rs1[0]));
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assign s2[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[2]);
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assign s2[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[1]);
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assign s2[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[0]);
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assign s3[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[2]);
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assign s3[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[1]);
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assign s3[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[0]);
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assign s1[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[2]) | (STORE & Rls[2]) | (PSH & Rs1[2]));
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assign s1[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[1]) | (STORE & Rls[1]) | (PSH & Rs1[1]));
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assign s1[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[0]) | (STORE & Rls[0]) | (PSH & Rs1[0]));
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assign s2[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rs2[2]);
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assign s2[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rs2[1]);
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assign s2[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rs2[0]);
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assign s3[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rd[2]);
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assign s3[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rd[1]);
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assign s3[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rd[0]);
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assign s4 = EXEC1 & ~(LOAD | STORE);
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assign RAMd_wren = EXEC1 & STORE;
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assign RAMd_en = EXEC1 & (STORE | LOAD);
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127
test.bdf
Normal file
127
test.bdf
Normal file
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@ -0,0 +1,127 @@
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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*/
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