Merge pull request #1 from supleed2/alu

Alu MUL, MLA and MLS fixed. LUT in multiply block fixed.

LUT.v

@@ -107,8 +107,8 @@ module LUT (
 		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
 		altsyncram_component.outdata_aclr_a = "NONE",
 		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
-		altsyncram_component.outdata_reg_b = "CLOCK0",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
 		altsyncram_component.power_up_uninitialized = "FALSE",
 		altsyncram_component.widthad_a = 8,
 		altsyncram_component.widthad_b = 8,
@@ -159,11 +159,11 @@ endmodule
 // Retrieval info: PRIVATE: MIFfilename STRING "LUTSquares.mif"
 // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
 // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
 // Retrieval info: PRIVATE: REGdata NUMERIC "1"
-// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
 // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
 // Retrieval info: PRIVATE: REGrren NUMERIC "0"
 // Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
@@ -196,8 +196,8 @@ endmodule
 // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
 // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
 // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
 // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
 // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
 // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
@@ -225,5 +225,5 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL LUT.cmp FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL LUT.bsf TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL LUT_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL LUT_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL LUT_bb.v TRUE
 // Retrieval info: LIB_FILE: altera_mf

alu.v

@@ -1,4 +1,4 @@
-module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, mul1, mul2, Rout, jump, carry);
+module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, mul1, mul2, Rout, jump, carry, jumpflags);
 
 input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
 input signed [15:0] Rd; // input destination register
@@ -14,6 +14,7 @@ output reg signed [15:0] mul2; // second number to be multiplied
 output signed [15:0] Rout; // value to be saved to destination register
 output jump; // tells decoder whether Jump condition is true
 output reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging
+output [7:0] jumpflags;
 
 reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
 assign Rout = alusum [15:0];
@@ -30,8 +31,9 @@ assign JC5 = (Rs1 >= Rs2);
 assign JC6 = (Rs1 <= Rs2);
 assign JC7 = (Rs1 != Rs2);
 assign JC8 = (Rs1 < 0);
+assign jumpflags = {JC1, JC2, JC3, JC4, JC5, JC6, JC7, JC8};
 
-always @(*)
+always @(opcode, mulresult)
 	begin
 		if(!enable) begin
 			case (opcode)
@@ -87,31 +89,65 @@ always @(*)
 				
 				6'b011100: begin // MUL Multiply (Rd = Rs1 * Rs2)
 						if(!exec2) begin
-								mul1 = Rs1;
+								if(Rs1[15]) begin
-								mul2 = Rs2;
+										mul1 = ~Rs1 + {16'h0001};
+									end
+								else begin
+										mul1 = Rs1;
+									end
+								if(Rs2[15]) begin
+										mul2 = ~Rs2 + {16'h0001};
+									end
+								else begin
+										mul2 = Rs2;
+									end
+								alusum = 17'b00000000000000000;
+								carry = (Rs1[15]^Rs2[15]) ? 1'b1 : 1'b0;
 							end
 						else begin
-								alusum[16] = 1'b0;
+								{mulextra, alusum[15:0]} = (carry) ? ~mulresult + 32'h00000001 : mulresult;
-								{mulextra, alusum[15:0]} = mulresult;
 							end
 					end
 				6'b011101: begin // MLA Multiply and Add  (Rd = Rs2 + (Rd * Rs1))
 						if(!exec2) begin
-								mul1 = Rs1;
+								if(Rd[15]) begin
-								mul2 = Rs2;
+										mul1 = ~Rd + {16'h0001};
+									end
+								else begin
+										mul1 = Rd;
+									end
+								if(Rs1[15]) begin
+										mul2 = ~Rs1 + {16'h0001};
+									end
+								else begin
+										mul2 = Rs1;
+									end
+								alusum = 17'b00000000000000000;
+								carry = (Rs1[15]^Rs2[15]) ? 1'b1 : 1'b0;
 							end
 						else begin
-								alusum[16] = 1'b0;
+								{mulextra, alusum[15:0]} = (carry) ? ~mulresult + 32'h00000001 + {16'h0000, Rs2} : mulresult + {16'h0000, Rs2};
-								{mulextra, alusum[15:0]} = mulresult + {16'h0000, Rs2};
 							end
 					end
 				6'b011110: begin // MLS Multiply and Subtract (Rd = Rs2 - (Rd * Rs1)[15:0])
 						if(!exec2) begin
-								mul1 = Rs1;
+								if(Rd[15]) begin
-								mul2 = Rs2;
+										mul1 = ~Rd + {16'h0001};
+									end
+								else begin
+										mul1 = Rd;
+									end
+								if(Rs1[15]) begin
+										mul2 = ~Rs1 + {16'h0001};
+									end
+								else begin
+										mul2 = Rs1;
+									end
+								alusum = 17'b00000000000000000;
+								carry = (Rs1[15]^Rs2[15]) ? 1'b1 : 1'b0;
 							end
 						else begin
-								alusum = {1'b0, Rs2 - mulresult[15:0]};
+								alusum = (carry) ? {1'b0, Rs2 - (~mulresult[15:0] + 16'h0001)} : {1'b0, Rs2 - mulresult[15:0]};
 							end
 					end
 				6'b011111: alusum = mulextra; // MRT Retrieve Multiply MSBs (Rd = MSBs)