diff --git a/CPUProject.bdf b/CPUProject.bdf
index 7f9edc9..ab580b4 100644
--- a/CPUProject.bdf
+++ b/CPUProject.bdf
@@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2018  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
+and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
@@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
 agreement, including, without limitation, that your use is for
 the sole purpose of programming logic devices manufactured by
 Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
+refer to the applicable agreement for further details.
 */
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-		(text "s4" (rect 178 219 187 231)(font "Arial" ))
-		(line (pt 208 224)(pt 192 224))
-	)
-	(port
-		(pt 208 240)
-		(output)
-		(text "RAMd_wren" (rect 0 0 57 12)(font "Arial" ))
-		(text "RAMd_wren" (rect 139 235 187 247)(font "Arial" ))
-		(line (pt 208 240)(pt 192 240))
-	)
-	(port
-		(pt 208 256)
-		(output)
-		(text "RAMd_en" (rect 0 0 47 12)(font "Arial" ))
-		(text "RAMd_en" (rect 148 251 187 263)(font "Arial" ))
-		(line (pt 208 256)(pt 192 256))
-	)
-	(port
-		(pt 208 272)
-		(output)
-		(text "RAMi_en" (rect 0 0 43 12)(font "Arial" ))
-		(text "RAMi_en" (rect 151 267 187 279)(font "Arial" ))
-		(line (pt 208 272)(pt 192 272))
-	)
-	(port
-		(pt 208 288)
-		(output)
-		(text "ALU_en" (rect 0 0 38 12)(font "Arial" ))
-		(text "ALU_en" (rect 155 283 187 295)(font "Arial" ))
-		(line (pt 208 288)(pt 192 288))
-	)
-	(port
-		(pt 208 304)
-		(output)
-		(text "E2" (rect 0 0 12 12)(font "Arial" ))
-		(text "E2" (rect 177 299 187 311)(font "Arial" ))
-		(line (pt 208 304)(pt 192 304))
-	)
-	(port
-		(pt 208 320)
-		(output)
-		(text "stack_en" (rect 0 0 44 12)(font "Arial" ))
-		(text "stack_en" (rect 150 315 187 327)(font "Arial" ))
-		(line (pt 208 320)(pt 192 320))
-	)
-	(port
-		(pt 208 336)
-		(output)
-		(text "stack_rst" (rect 0 0 46 12)(font "Arial" ))
-		(text "stack_rst" (rect 149 331 187 343)(font "Arial" ))
-		(line (pt 208 336)(pt 192 336))
-	)
-	(port
-		(pt 208 352)
-		(output)
-		(text "stack_rw" (rect 0 0 43 12)(font "Arial" ))
-		(text "stack_rw" (rect 151 347 187 359)(font "Arial" ))
-		(line (pt 208 352)(pt 192 352))
-	)
-	(drawing
-		(rectangle (rect 16 16 192 384))
-	)
-)
 (symbol
 	(rect 928 320 1184 512)
 	(text "ALU_top" (rect 5 0 56 19)(font "Intel Clear" (font_size 8)))
@@ -1892,10 +1701,58 @@ https://fpgasoftware.intel.com/eula.
 		(line (pt 0 0)(pt 0 0))
 	)
 )
+(symbol
+	(rect 1256 272 1368 360)
+	(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
+	(text "MUX4" (rect 3 77 36 91)(font "Arial" (font_size 8)))
+	(port
+		(pt 0 64)
+		(input)
+		(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
+		(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 44 64)(line_width 3))
+	)
+	(port
+		(pt 56 88)
+		(input)
+		(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
+		(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
+		(line (pt 56 88)(pt 56 72))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
+		(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 44 32)(line_width 3))
+	)
+	(port
+		(pt 112 48)
+		(output)
+		(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
+		(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
+		(line (pt 68 48)(pt 112 48)(line_width 3))
+	)
+	(parameter
+		"WIDTH"
+		"16"
+		"Width of I/O, any integer > 0"
+		" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64" 
+	)
+	(drawing
+		(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
+		(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
+		(line (pt 68 64)(pt 68 32))
+		(line (pt 44 80)(pt 44 16))
+		(line (pt 44 16)(pt 68 32))
+		(line (pt 44 80)(pt 68 64))
+	)
+	(annotation_block (parameter)(rect 1368 272 1400 288))
+)
 (symbol
 	(rect 968 24 1080 112)
 	(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
-	(text "indirmux" (rect 3 77 43 94)(font "Intel Clear" ))
+	(text "MUX5" (rect 3 77 32 94)(font "Intel Clear" ))
 	(port
 		(pt 0 64)
 		(input)
@@ -1940,6 +1797,203 @@ https://fpgasoftware.intel.com/eula.
 	)
 	(annotation_block (parameter)(rect 1080 24 1112 48))
 )
+(symbol
+	(rect 1168 -184 1376 216)
+	(text "DECODE" (rect 5 0 52 12)(font "Arial" ))
+	(text "DECODE" (rect 8 384 55 396)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "instr[15..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "instr[15..0]" (rect 21 27 74 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "FETCH" (rect 0 0 36 12)(font "Arial" ))
+		(text "FETCH" (rect 21 43 57 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "EXEC1" (rect 0 0 34 12)(font "Arial" ))
+		(text "EXEC1" (rect 21 59 55 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "EXEC2" (rect 0 0 34 12)(font "Arial" ))
+		(text "EXEC2" (rect 21 75 55 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "COND_result" (rect 0 0 66 12)(font "Arial" ))
+		(text "COND_result" (rect 21 91 87 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96))
+	)
+	(port
+		(pt 208 32)
+		(output)
+		(text "R0_count" (rect 0 0 47 12)(font "Arial" ))
+		(text "R0_count" (rect 148 27 187 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32))
+	)
+	(port
+		(pt 208 48)
+		(output)
+		(text "R0_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R0_en" (rect 161 43 187 55)(font "Arial" ))
+		(line (pt 208 48)(pt 192 48))
+	)
+	(port
+		(pt 208 64)
+		(output)
+		(text "R1_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R1_en" (rect 161 59 187 71)(font "Arial" ))
+		(line (pt 208 64)(pt 192 64))
+	)
+	(port
+		(pt 208 80)
+		(output)
+		(text "R2_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R2_en" (rect 161 75 187 87)(font "Arial" ))
+		(line (pt 208 80)(pt 192 80))
+	)
+	(port
+		(pt 208 96)
+		(output)
+		(text "R3_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R3_en" (rect 161 91 187 103)(font "Arial" ))
+		(line (pt 208 96)(pt 192 96))
+	)
+	(port
+		(pt 208 112)
+		(output)
+		(text "R4_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R4_en" (rect 161 107 187 119)(font "Arial" ))
+		(line (pt 208 112)(pt 192 112))
+	)
+	(port
+		(pt 208 128)
+		(output)
+		(text "R5_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R5_en" (rect 161 123 187 135)(font "Arial" ))
+		(line (pt 208 128)(pt 192 128))
+	)
+	(port
+		(pt 208 144)
+		(output)
+		(text "R6_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R6_en" (rect 161 139 187 151)(font "Arial" ))
+		(line (pt 208 144)(pt 192 144))
+	)
+	(port
+		(pt 208 160)
+		(output)
+		(text "R7_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R7_en" (rect 161 155 187 167)(font "Arial" ))
+		(line (pt 208 160)(pt 192 160))
+	)
+	(port
+		(pt 208 176)
+		(output)
+		(text "s1[2..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "s1[2..0]" (rect 156 171 187 183)(font "Arial" ))
+		(line (pt 208 176)(pt 192 176)(line_width 3))
+	)
+	(port
+		(pt 208 192)
+		(output)
+		(text "s2[2..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "s2[2..0]" (rect 156 187 187 199)(font "Arial" ))
+		(line (pt 208 192)(pt 192 192)(line_width 3))
+	)
+	(port
+		(pt 208 208)
+		(output)
+		(text "s3[2..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "s3[2..0]" (rect 156 203 187 215)(font "Arial" ))
+		(line (pt 208 208)(pt 192 208)(line_width 3))
+	)
+	(port
+		(pt 208 224)
+		(output)
+		(text "s4" (rect 0 0 11 12)(font "Arial" ))
+		(text "s4" (rect 178 219 187 231)(font "Arial" ))
+		(line (pt 208 224)(pt 192 224))
+	)
+	(port
+		(pt 208 240)
+		(output)
+		(text "RAMd_wren" (rect 0 0 57 12)(font "Arial" ))
+		(text "RAMd_wren" (rect 139 235 187 247)(font "Arial" ))
+		(line (pt 208 240)(pt 192 240))
+	)
+	(port
+		(pt 208 256)
+		(output)
+		(text "RAMd_en" (rect 0 0 47 12)(font "Arial" ))
+		(text "RAMd_en" (rect 148 251 187 263)(font "Arial" ))
+		(line (pt 208 256)(pt 192 256))
+	)
+	(port
+		(pt 208 272)
+		(output)
+		(text "RAMi_en" (rect 0 0 43 12)(font "Arial" ))
+		(text "RAMi_en" (rect 151 267 187 279)(font "Arial" ))
+		(line (pt 208 272)(pt 192 272))
+	)
+	(port
+		(pt 208 288)
+		(output)
+		(text "ALU_en" (rect 0 0 38 12)(font "Arial" ))
+		(text "ALU_en" (rect 155 283 187 295)(font "Arial" ))
+		(line (pt 208 288)(pt 192 288))
+	)
+	(port
+		(pt 208 304)
+		(output)
+		(text "E2" (rect 0 0 12 12)(font "Arial" ))
+		(text "E2" (rect 177 299 187 311)(font "Arial" ))
+		(line (pt 208 304)(pt 192 304))
+	)
+	(port
+		(pt 208 320)
+		(output)
+		(text "stack_en" (rect 0 0 44 12)(font "Arial" ))
+		(text "stack_en" (rect 150 315 187 327)(font "Arial" ))
+		(line (pt 208 320)(pt 192 320))
+	)
+	(port
+		(pt 208 336)
+		(output)
+		(text "stack_rst" (rect 0 0 46 12)(font "Arial" ))
+		(text "stack_rst" (rect 149 331 187 343)(font "Arial" ))
+		(line (pt 208 336)(pt 192 336))
+	)
+	(port
+		(pt 208 352)
+		(output)
+		(text "stack_rw" (rect 0 0 43 12)(font "Arial" ))
+		(text "stack_rw" (rect 151 347 187 359)(font "Arial" ))
+		(line (pt 208 352)(pt 192 352))
+	)
+	(port
+		(pt 208 368)
+		(output)
+		(text "s5" (rect 0 0 11 12)(font "Arial" ))
+		(text "s5" (rect 178 363 187 375)(font "Arial" ))
+		(line (pt 208 368)(pt 192 368))
+	)
+	(drawing
+		(rectangle (rect 16 16 192 384))
+	)
+)
 (connector
 	(pt 856 192)
 	(pt 936 192)
@@ -2315,114 +2369,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 1416 792)
 	(bus)
 )
-(connector
-	(pt 1152 192)
-	(pt 1160 192)
-	(bus)
-)
-(connector
-	(text "R0_count" (rect 1386 -120 1430 -103)(font "Intel Clear" ))
-	(pt 1376 -104)
-	(pt 1424 -104)
-)
-(connector
-	(text "R0_en" (rect 1386 -104 1416 -87)(font "Intel Clear" ))
-	(pt 1376 -88)
-	(pt 1424 -88)
-)
-(connector
-	(text "R1_en" (rect 1386 -88 1416 -71)(font "Intel Clear" ))
-	(pt 1376 -72)
-	(pt 1424 -72)
-)
-(connector
-	(text "R2_en" (rect 1386 -72 1416 -55)(font "Intel Clear" ))
-	(pt 1376 -56)
-	(pt 1424 -56)
-)
-(connector
-	(text "R3_en" (rect 1386 -56 1416 -39)(font "Intel Clear" ))
-	(pt 1376 -40)
-	(pt 1424 -40)
-)
-(connector
-	(text "R4_en" (rect 1386 -40 1416 -23)(font "Intel Clear" ))
-	(pt 1376 -24)
-	(pt 1424 -24)
-)
-(connector
-	(text "R5_en" (rect 1386 -24 1416 -7)(font "Intel Clear" ))
-	(pt 1376 -8)
-	(pt 1424 -8)
-)
-(connector
-	(text "R6_en" (rect 1386 -8 1416 9)(font "Intel Clear" ))
-	(pt 1376 8)
-	(pt 1424 8)
-)
-(connector
-	(text "R7_en" (rect 1386 8 1416 25)(font "Intel Clear" ))
-	(pt 1376 24)
-	(pt 1424 24)
-)
-(connector
-	(text "s1[2..0]" (rect 1386 24 1420 41)(font "Intel Clear" ))
-	(pt 1376 40)
-	(pt 1424 40)
-	(bus)
-)
-(connector
-	(text "s2[2..0]" (rect 1386 40 1420 57)(font "Intel Clear" ))
-	(pt 1376 56)
-	(pt 1424 56)
-	(bus)
-)
-(connector
-	(text "s3[2..0]" (rect 1386 56 1420 73)(font "Intel Clear" ))
-	(pt 1376 72)
-	(pt 1424 72)
-	(bus)
-)
-(connector
-	(text "RAMd_wren" (rect 1386 88 1445 105)(font "Intel Clear" ))
-	(pt 1376 104)
-	(pt 1440 104)
-)
-(connector
-	(text "RAMd_en" (rect 1386 104 1433 121)(font "Intel Clear" ))
-	(pt 1376 120)
-	(pt 1424 120)
-)
-(connector
-	(text "RAMi_en" (rect 1386 120 1429 137)(font "Intel Clear" ))
-	(pt 1376 136)
-	(pt 1424 136)
-)
-(connector
-	(text "ALU_en" (rect 1386 136 1423 153)(font "Intel Clear" ))
-	(pt 1376 152)
-	(pt 1424 152)
-)
-(connector
-	(text "E2" (rect 1386 152 1397 169)(font "Intel Clear" ))
-	(pt 1376 168)
-	(pt 1424 168)
-)
-(connector
-	(text "stack_en" (rect 1386 168 1428 185)(font "Intel Clear" ))
-	(pt 1376 184)
-	(pt 1424 184)
-)
-(connector
-	(text "stack_rst" (rect 1386 184 1428 201)(font "Intel Clear" ))
-	(pt 1376 200)
-	(pt 1424 200)
-)
-(connector
-	(text "stack_rw" (rect 1386 200 1428 217)(font "Intel Clear" ))
-	(pt 1376 216)
-	(pt 1424 216)
-)
 (connector
 	(text "Rs1[15..0]" (rect 818 160 865 177)(font "Intel Clear" ))
 	(pt 816 176)
@@ -2583,26 +2529,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 344 728)
 	(pt 392 728)
 )
-(connector
-	(text "EXEC1" (rect 1138 -88 1169 -71)(font "Intel Clear" ))
-	(pt 1128 -72)
-	(pt 1168 -72)
-)
-(connector
-	(text "EXEC2" (rect 1138 -72 1169 -55)(font "Intel Clear" ))
-	(pt 1128 -56)
-	(pt 1168 -56)
-)
-(connector
-	(text "COND" (rect 1138 -56 1167 -39)(font "Intel Clear" ))
-	(pt 1128 -40)
-	(pt 1168 -40)
-)
-(connector
-	(text "FETCH" (rect 1138 -104 1169 -87)(font "Intel Clear" ))
-	(pt 1168 -88)
-	(pt 1128 -88)
-)
 (connector
 	(text "CLK" (rect 578 88 598 105)(font "Intel Clear" ))
 	(pt 568 104)
@@ -2613,12 +2539,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 560 120)
 	(pt 600 120)
 )
-(connector
-	(text "instr[15..0]" (rect 882 -120 931 -103)(font "Intel Clear" ))
-	(pt 872 -104)
-	(pt 1168 -104)
-	(bus)
-)
 (connector
 	(text "ALU_out[15..0]" (rect 1448 264 1518 281)(font "Intel Clear" ))
 	(pt 1440 280)
@@ -2636,32 +2556,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 1512 328)
 	(pt 1440 328)
 )
-(connector
-	(text "Rs1[15..0]" (rect 850 624 897 641)(font "Intel Clear" ))
-	(pt 840 640)
-	(pt 896 640)
-	(bus)
-)
-(connector
-	(text "CLK" (rect 850 640 870 657)(font "Intel Clear" ))
-	(pt 840 656)
-	(pt 896 656)
-)
-(connector
-	(text "stack_en" (rect 850 656 892 673)(font "Intel Clear" ))
-	(pt 840 672)
-	(pt 896 672)
-)
-(connector
-	(text "stack_rst" (rect 850 672 892 689)(font "Intel Clear" ))
-	(pt 840 688)
-	(pt 896 688)
-)
-(connector
-	(text "stack_rw" (rect 850 688 892 705)(font "Intel Clear" ))
-	(pt 840 704)
-	(pt 896 704)
-)
 (connector
 	(pt 1416 320)
 	(pt 1368 320)
@@ -2677,33 +2571,11 @@ https://fpgasoftware.intel.com/eula.
 	(pt 1416 792)
 	(bus)
 )
-(connector
-	(pt 1160 192)
-	(pt 1160 304)
-	(bus)
-)
-(connector
-	(text "RAMd_out[15..0]" (rect 1178 288 1258 305)(font "Intel Clear" ))
-	(pt 1160 304)
-	(pt 1256 304)
-	(bus)
-)
-(connector
-	(text "stack_out[15..0]" (rect 1082 624 1157 641)(font "Intel Clear" ))
-	(pt 1080 640)
-	(pt 1144 640)
-	(bus)
-)
 (connector
 	(text "s4" (rect 1296 373 1313 383)(font "Intel Clear" )(vertical))
 	(pt 1312 360)
 	(pt 1312 392)
 )
-(connector
-	(text "s4" (rect 1386 72 1396 89)(font "Intel Clear" ))
-	(pt 1376 88)
-	(pt 1424 88)
-)
 (connector
 	(text "SM_rst" (rect 354 696 387 713)(font "Intel Clear" ))
 	(pt 344 712)
@@ -2909,16 +2781,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 872 464)
 	(bus)
 )
-(connector
-	(pt 872 -104)
-	(pt 872 24)
-	(bus)
-)
-(connector
-	(pt 872 24)
-	(pt 872 56)
-	(bus)
-)
 (connector
 	(text "instr[10..0]" (rect 904 40 953 57)(font "Intel Clear" ))
 	(pt 872 56)
@@ -2968,16 +2830,234 @@ https://fpgasoftware.intel.com/eula.
 	(pt 872 152)
 	(bus)
 )
-(connector
-	(pt 1024 112)
-	(pt 1024 136)
-)
 (connector
 	(text "memaddr[10..0]" (rect 1448 392 1523 409)(font "Intel Clear" ))
 	(pt 1512 408)
 	(pt 1440 408)
 	(bus)
 )
+(connector
+	(text "s5" (rect 1008 117 1025 127)(font "Intel Clear" )(vertical))
+	(pt 1024 112)
+	(pt 1024 136)
+)
+(connector
+	(pt 1152 192)
+	(pt 1160 192)
+	(bus)
+)
+(connector
+	(text "R0_count" (rect 1386 -168 1430 -151)(font "Intel Clear" ))
+	(pt 1376 -152)
+	(pt 1424 -152)
+)
+(connector
+	(text "R0_en" (rect 1386 -152 1416 -135)(font "Intel Clear" ))
+	(pt 1376 -136)
+	(pt 1424 -136)
+)
+(connector
+	(text "R1_en" (rect 1386 -136 1416 -119)(font "Intel Clear" ))
+	(pt 1376 -120)
+	(pt 1424 -120)
+)
+(connector
+	(text "R2_en" (rect 1386 -120 1416 -103)(font "Intel Clear" ))
+	(pt 1376 -104)
+	(pt 1424 -104)
+)
+(connector
+	(text "R3_en" (rect 1386 -104 1416 -87)(font "Intel Clear" ))
+	(pt 1376 -88)
+	(pt 1424 -88)
+)
+(connector
+	(text "R4_en" (rect 1386 -88 1416 -71)(font "Intel Clear" ))
+	(pt 1376 -72)
+	(pt 1424 -72)
+)
+(connector
+	(text "R5_en" (rect 1386 -72 1416 -55)(font "Intel Clear" ))
+	(pt 1376 -56)
+	(pt 1424 -56)
+)
+(connector
+	(text "R6_en" (rect 1386 -56 1416 -39)(font "Intel Clear" ))
+	(pt 1376 -40)
+	(pt 1424 -40)
+)
+(connector
+	(text "R7_en" (rect 1386 -40 1416 -23)(font "Intel Clear" ))
+	(pt 1376 -24)
+	(pt 1424 -24)
+)
+(connector
+	(text "s1[2..0]" (rect 1386 -24 1420 -7)(font "Intel Clear" ))
+	(pt 1376 -8)
+	(pt 1424 -8)
+	(bus)
+)
+(connector
+	(text "s2[2..0]" (rect 1386 -8 1420 9)(font "Intel Clear" ))
+	(pt 1376 8)
+	(pt 1424 8)
+	(bus)
+)
+(connector
+	(text "s3[2..0]" (rect 1386 8 1420 25)(font "Intel Clear" ))
+	(pt 1376 24)
+	(pt 1424 24)
+	(bus)
+)
+(connector
+	(text "RAMd_en" (rect 1386 56 1433 73)(font "Intel Clear" ))
+	(pt 1376 72)
+	(pt 1424 72)
+)
+(connector
+	(text "RAMi_en" (rect 1386 72 1429 89)(font "Intel Clear" ))
+	(pt 1376 88)
+	(pt 1424 88)
+)
+(connector
+	(text "E2" (rect 1386 104 1397 121)(font "Intel Clear" ))
+	(pt 1376 120)
+	(pt 1424 120)
+)
+(connector
+	(text "stack_en" (rect 1386 120 1428 137)(font "Intel Clear" ))
+	(pt 1376 136)
+	(pt 1424 136)
+)
+(connector
+	(text "stack_rst" (rect 1386 136 1428 153)(font "Intel Clear" ))
+	(pt 1376 152)
+	(pt 1424 152)
+)
+(connector
+	(text "stack_rw" (rect 1386 152 1428 169)(font "Intel Clear" ))
+	(pt 1376 168)
+	(pt 1424 168)
+)
+(connector
+	(text "EXEC1" (rect 1138 -136 1169 -119)(font "Intel Clear" ))
+	(pt 1128 -120)
+	(pt 1168 -120)
+)
+(connector
+	(text "EXEC2" (rect 1138 -120 1169 -103)(font "Intel Clear" ))
+	(pt 1128 -104)
+	(pt 1168 -104)
+)
+(connector
+	(text "COND" (rect 1138 -104 1167 -87)(font "Intel Clear" ))
+	(pt 1128 -88)
+	(pt 1168 -88)
+)
+(connector
+	(text "FETCH" (rect 1138 -152 1169 -135)(font "Intel Clear" ))
+	(pt 1168 -136)
+	(pt 1128 -136)
+)
+(connector
+	(text "instr[15..0]" (rect 882 -168 931 -151)(font "Intel Clear" ))
+	(pt 872 -152)
+	(pt 1168 -152)
+	(bus)
+)
+(connector
+	(pt 1160 192)
+	(pt 1160 304)
+	(bus)
+)
+(connector
+	(text "RAMd_out[15..0]" (rect 1178 288 1258 305)(font "Intel Clear" ))
+	(pt 1256 304)
+	(pt 1160 304)
+	(bus)
+)
+(connector
+	(text "s4" (rect 1386 24 1396 41)(font "Intel Clear" ))
+	(pt 1376 40)
+	(pt 1424 40)
+)
+(connector
+	(pt 872 -152)
+	(pt 872 24)
+	(bus)
+)
+(connector
+	(pt 872 24)
+	(pt 872 56)
+	(bus)
+)
+(connector
+	(text "RAMd_wren" (rect 1386 40 1445 57)(font "Intel Clear" ))
+	(pt 1376 56)
+	(pt 1440 56)
+)
+(connector
+	(text "ALU_en" (rect 1386 88 1423 105)(font "Intel Clear" ))
+	(pt 1376 104)
+	(pt 1424 104)
+)
+(connector
+	(text "Rs1[15..0]" (rect 850 600 897 617)(font "Intel Clear" ))
+	(pt 840 616)
+	(pt 896 616)
+	(bus)
+)
+(connector
+	(text "CLK" (rect 850 616 870 633)(font "Intel Clear" ))
+	(pt 840 632)
+	(pt 896 632)
+)
+(connector
+	(text "stack_en" (rect 850 632 892 649)(font "Intel Clear" ))
+	(pt 840 648)
+	(pt 896 648)
+)
+(connector
+	(text "stack_rst" (rect 850 648 892 665)(font "Intel Clear" ))
+	(pt 840 664)
+	(pt 896 664)
+)
+(connector
+	(text "stack_rw" (rect 850 664 892 681)(font "Intel Clear" ))
+	(pt 840 680)
+	(pt 896 680)
+)
+(connector
+	(text "stack_out[15..0]" (rect 1082 600 1157 617)(font "Intel Clear" ))
+	(pt 1080 616)
+	(pt 1144 616)
+	(bus)
+)
+(connector
+	(text "stack_empty" (rect 1082 616 1143 633)(font "Intel Clear" ))
+	(pt 1080 632)
+	(pt 1144 632)
+)
+(connector
+	(text "stack_full" (rect 1082 632 1129 649)(font "Intel Clear" ))
+	(pt 1080 648)
+	(pt 1144 648)
+)
+(connector
+	(text "stack_empty" (rect 1450 408 1511 425)(font "Intel Clear" ))
+	(pt 1512 424)
+	(pt 1440 424)
+)
+(connector
+	(text "stack_full" (rect 1450 424 1497 441)(font "Intel Clear" ))
+	(pt 1512 440)
+	(pt 1440 440)
+)
+(connector
+	(text "s5" (rect 1386 168 1396 185)(font "Intel Clear" ))
+	(pt 1376 184)
+	(pt 1424 184)
+)
 (junction (pt 856 192))
 (junction (pt 136 320))
 (junction (pt 136 352))
diff --git a/CPUProject.qsf b/CPUProject.qsf
index f6d4eb8..1e223f9 100644
--- a/CPUProject.qsf
+++ b/CPUProject.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE AUTO
 set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11  MAY 20, 2020"
-set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
diff --git a/CPUProject.qws b/CPUProject.qws
new file mode 100644
index 0000000..23e7964
Binary files /dev/null and b/CPUProject.qws differ
diff --git a/DECODE.bsf b/DECODE.bsf
index 7507f83..7a4bebf 100644
--- a/DECODE.bsf
+++ b/DECODE.bsf
@@ -205,6 +205,13 @@ refer to the applicable agreement for further details.
 		(text "stack_rw" (rect 151 347 187 359)(font "Arial" ))
 		(line (pt 208 352)(pt 192 352)(line_width 1))
 	)
+	(port
+		(pt 208 368)
+		(output)
+		(text "s5" (rect 0 0 9 12)(font "Arial" ))
+		(text "s5" (rect 178 363 187 375)(font "Arial" ))
+		(line (pt 208 368)(pt 192 368)(line_width 1))
+	)
 	(drawing
 		(rectangle (rect 16 16 192 384)(line_width 1))
 	)
diff --git a/DECODE.v b/DECODE.v
index 6717c52..d0f2da1 100644
--- a/DECODE.v
+++ b/DECODE.v
@@ -25,58 +25,62 @@ module DECODE
 	output E2,
 	output stack_en,
 	output stack_rst,
-	output stack_rw
+	output stack_rw,
+	output s5
 );
 
 	wire msb = instr[15];					//MSB of the instruction word
-	wire ls = instr[14];						//LOAD or STORE bit
-	wire [2:0] Rls = instr[13:11];		//Register in the LOAD/STORE operation
-	wire [10:0] addr = instr[10:0];		//Memory address in the LOAD/STORE operation
+	wire ls = instr[14];						//LDA or STA bit
+	wire [2:0] Rls = instr[13:11];		//Register in the LDA/STA operation
+	wire [10:0] addr = instr[10:0];		//Memory address in the LDA/STA operation
 	wire [5:0] op = instr[14:9];			//Opcode in regular instructions
 	wire [2:0] Rd = instr[8:6];			//Destination register in command
 	wire [2:0] Rs1 = instr[5:3];			//Source register 1 in command
 	wire [2:0] Rs2 = instr[2:0];			//Source register 2 in command
 	
 	//Different opcodes (refer to documentation):
-	wire LOAD = msb & ~ls;
-	wire STORE = msb & ls;
-	wire UJMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2];
-	wire JMP = ~msb & ((~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]));
+	wire LDA =  msb & ~ls;
+	wire STA =  msb &  ls;
+	wire JMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2];
+	wire JCX = ~msb & ((~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]));
 	wire MUL = ~msb & ~op[5] &  op[4] &  op[3] &  op[2] & ~op[1] & ~op[0];
 	wire MLA = ~msb & ~op[5] &  op[4] &  op[3] &  op[2] & ~op[1] &  op[0];
 	wire MLS = ~msb & ~op[5] &  op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
 	wire PSH = ~msb &  op[5] & ~op[4] &  op[3] & ~op[2] & ~op[1] & ~op[0];
 	wire POP = ~msb &  op[5] & ~op[4] &  op[3] & ~op[2] & ~op[1] &  op[0];
+	wire LDR = ~msb &  op[5] & ~op[4] &  op[3] & ~op[2] &  op[1] & ~op[0];
+	wire STR = ~msb &  op[5] & ~op[4] &  op[3] & ~op[2] &  op[1] &  op[0];
 	wire NOP = ~msb &  op[5] &  op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
 	wire STP = ~msb &  op[5] &  op[4] &  op[3] &  op[2] &  op[1] &  op[0];
 	
-	assign R0_count = EXEC1 & (~(UJMP | (JMP & COND_result) | STP));
-	assign R0_en = (EXEC1 & (~(STORE | NOP | STP | LOAD | PSH) & ~Rd[2] & ~Rd[1] & ~Rd[0] | UJMP | JMP & COND_result)) | (EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & ~Rd[0]);
-	assign R1_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] & ~Rd[1] &  Rd[0]) | (EXEC2 & LOAD & ~Rls[2] & ~Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] &  Rd[0]);
-	assign R2_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] &  Rd[1] & ~Rd[0]) | (EXEC2 & LOAD & ~Rls[2] &  Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] &  Rd[1] & ~Rd[0]);
-	assign R3_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] &  Rd[1] &  Rd[0]) | (EXEC2 & LOAD & ~Rls[2] &  Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] &  Rd[1] &  Rd[0]);
-	assign R4_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) &  Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LOAD &  Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) &  Rd[2] & ~Rd[1] & ~Rd[0]);
-	assign R5_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) &  Rd[2] & ~Rd[1] &  Rd[0]) | (EXEC2 & LOAD &  Rls[2] & ~Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) &  Rd[2] & ~Rd[1] &  Rd[0]);
-	assign R6_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) &  Rd[2] &  Rd[1] & ~Rd[0]) | (EXEC2 & LOAD &  Rls[2] &  Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) &  Rd[2] &  Rd[1] & ~Rd[0]);
-	assign R7_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) &  Rd[2] &  Rd[1] &  Rd[0]) | (EXEC2 & LOAD &  Rls[2] &  Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) &  Rd[2] &  Rd[1] &  Rd[0]);
-	assign s1[2] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[2]) | (STORE & Rls[2]) | (PSH & Rs1[2]);
-	assign s1[1] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[1]) | (STORE & Rls[1]) | (PSH & Rs1[1]);
-	assign s1[0] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[0]) | (STORE & Rls[0]) | (PSH & Rs1[0]);
-	assign s2[2] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[2]);
-	assign s2[1] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[1]);
-	assign s2[0] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[0]);
-	assign s3[2] = (~(STORE | LOAD | NOP | STP | PSH | POP) & Rd[2]);
-	assign s3[1] = (~(STORE | LOAD | NOP | STP | PSH | POP) & Rd[1]);
-	assign s3[0] = (~(STORE | LOAD | NOP | STP | PSH | POP) & Rd[0]);
-	assign s4 = ~LOAD;
-	assign RAMd_wren = EXEC1 & STORE;
-	assign RAMd_en = EXEC1 & (STORE | LOAD);
+	assign R0_count = EXEC1 & (~(JMP | (JCX & COND_result) | STP));
+	assign R0_en = (EXEC1 & (~(STA | NOP | STP | LDA | PSH) & ~Rd[2] & ~Rd[1] & ~Rd[0] | JMP | JCX & COND_result)) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & ~Rd[2] & ~Rd[1] & ~Rd[0]);
+	assign R1_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] & ~Rd[1] &  Rd[0]) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & ~Rd[2] & ~Rd[1] &  Rd[0]);
+	assign R2_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] &  Rd[1] & ~Rd[0]) | (EXEC2 & LDA & ~Rls[2] &  Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & ~Rd[2] &  Rd[1] & ~Rd[0]);
+	assign R3_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] &  Rd[1] &  Rd[0]) | (EXEC2 & LDA & ~Rls[2] &  Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & ~Rd[2] &  Rd[1] &  Rd[0]);
+	assign R4_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) &  Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LDA &  Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) &  Rd[2] & ~Rd[1] & ~Rd[0]);
+	assign R5_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) &  Rd[2] & ~Rd[1] &  Rd[0]) | (EXEC2 & LDA &  Rls[2] & ~Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) &  Rd[2] & ~Rd[1] &  Rd[0]);
+	assign R6_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) &  Rd[2] &  Rd[1] & ~Rd[0]) | (EXEC2 & LDA &  Rls[2] &  Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) &  Rd[2] &  Rd[1] & ~Rd[0]);
+	assign R7_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) &  Rd[2] &  Rd[1] &  Rd[0]) | (EXEC2 & LDA &  Rls[2] &  Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) &  Rd[2] &  Rd[1] &  Rd[0]);
+	assign s1[2] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[2]) | (STA & Rls[2]);
+	assign s1[1] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[1]) | (STA & Rls[1]);
+	assign s1[0] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[0]) | (STA & Rls[0]);
+	assign s2[2] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[2]);
+	assign s2[1] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[1]);
+	assign s2[0] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[0]);
+	assign s3[2] = (~(STA | LDA | NOP | STP | PSH | POP | LDR) & Rd[2]);
+	assign s3[1] = (~(STA | LDA | NOP | STP | PSH | POP | LDR) & Rd[1]);
+	assign s3[0] = (~(STA | LDA | NOP | STP | PSH | POP | LDR) & Rd[0]);
+	assign s4 = ~(LDA | LDR);
+	assign RAMd_wren = EXEC1 & (STA | STR);
+	assign RAMd_en = EXEC1 & (STA | LDA | STR | LDR);
 	assign RAMi_en = FETCH;
-	assign ALU_en = LOAD | STORE;
-	assign E2 = EXEC1 & (LOAD | MUL | MLA | MLS | POP);
+	assign ALU_en = LDA | STA;
+	assign E2 = EXEC1 & (LDA | MUL | MLA | MLS | POP);
 	assign stack_en = (EXEC1 & PSH) | ((EXEC1 | EXEC2) & POP);
 	assign stack_rst = STP;
 	assign stack_rw = EXEC1 & PSH;
+	assign s5 = (EXEC1 & STR) | (EXEC2 & LDR);
 	
 endmodule
 	
\ No newline at end of file