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Remove debug lines from ALU to improve performance

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This commit is contained in:
Aadi Desai 2020-06-11 16:23:16 +01:00
parent d6bb9bd762
commit 6c1f7fc59b
1 changed files with 2 additions and 8 deletions
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10
alu.v
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@ -1,4 +1,4 @@
module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, memdatain, mul1, mul2, Rout, jump, carry, jumpflags, memaddr); module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, mul1, mul2, Rout, jump, memaddr);
input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
input signed [15:0] Rs1; // input source register 1 input signed [15:0] Rs1; // input source register 1
@ -8,14 +8,12 @@ input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
input signed [31:0] mulresult; // 32-bit result from multiplier input signed [31:0] mulresult; // 32-bit result from multiplier
input exec2; // Input from state machine to indicate when to take in result from multiplication input exec2; // Input from state machine to indicate when to take in result from multiplication
input [15:0] stackout; // input from stack to be fed back to registers input [15:0] stackout; // input from stack to be fed back to registers
input signed [15:0] memdatain; // input data from RAMd
output reg signed [15:0] mul1; // first number to be multiplied output reg signed [15:0] mul1; // first number to be multiplied
output reg signed [15:0] mul2; // second number to be multiplied output reg signed [15:0] mul2; // second number to be multiplied
output signed [15:0] Rout; // value to be saved to destination register output signed [15:0] Rout; // value to be saved to destination register
output jump; // tells decoder whether Jump condition is true output jump; // tells decoder whether Jump condition is true
output reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging reg carry; // Internal carry register that is updated during appropriate opcodes
output [7:0] jumpflags;
output reg [10:0] memaddr; // address to load data from / store data to RAMd output reg [10:0] memaddr; // address to load data from / store data to RAMd
reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
@ -33,7 +31,6 @@ assign JC5 = (Rs1 >= Rs2);
assign JC6 = (Rs1 <= Rs2); assign JC6 = (Rs1 <= Rs2);
assign JC7 = (Rs1 != Rs2); assign JC7 = (Rs1 != Rs2);
assign JC8 = (Rs1 < 0); assign JC8 = (Rs1 < 0);
assign jumpflags = {JC1, JC2, JC3, JC4, JC5, JC6, JC7, JC8};
always @(opcode, mulresult) always @(opcode, mulresult)
begin begin
@ -170,9 +167,6 @@ always @(opcode, mulresult)
if(!exec2) begin if(!exec2) begin
memaddr = Rs1[10:0]; memaddr = Rs1[10:0];
end end
else begin
alusum = {1'b0, memdatain};
end
end end
6'b101011: begin // STR Indirect Store (Mem[Rd] = Rs1) 6'b101011: begin // STR Indirect Store (Mem[Rd] = Rs1)
memaddr = Rd[10:0]; memaddr = Rd[10:0];