Working on initial design

This commit is contained in:
Kacper 2020-05-25 17:16:24 +01:00
parent 14418c8725
commit 6b2363d6a1
7 changed files with 2860 additions and 283 deletions

View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2019 Intel Corporation. All rights reserved. Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,115 +16,196 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at refer to the applicable agreement for further details.
https://fpgasoftware.intel.com/eula.
*/ */
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View file

@ -38,16 +38,17 @@
set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE AUTO set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY CPUProject set_global_assignment -name TOP_LEVEL_ENTITY reg_file
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020" set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BDF_FILE CPUProject.bdf set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf set_global_assignment -name BDF_FILE CPUProject.bdf
set_global_assignment -name BDF_FILE reg_file.bdf
set_global_assignment -name BDF_FILE mux_8x16.bdf

View file

@ -1,178 +0,0 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off CPUProject -c CPUProject --vector_source="C:/Users/Benjamin/Desktop/CPUProject/Waveform.vwf" --testbench_file="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off CPUProject -c CPUProject --vector_source="C:/Users/Benjamin/Desktop/CPUProject/Waveform.vwf" --testbench_file="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/" CPUProject -c CPUProject</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/" CPUProject -c CPUProject</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vlog -work work CPUProject.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.CPUProject_vlg_vec_tst
vcd file -direction CPUProject.msim.vcd
vcd add -internal CPUProject_vlg_vec_tst/*
vcd add -internal CPUProject_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vlog -work work CPUProject.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.CPUProject_vlg_vec_tst
vcd file -direction CPUProject.msim.vcd
vcd add -internal CPUProject_vlg_vec_tst/*
vcd add -internal CPUProject_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
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VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
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SIGNAL("Y")
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VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("Z")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
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NODE
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NODE
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REPEAT = 50;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
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}
}
TRANSITION_LIST("Y")
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NODE
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REPEAT = 1;
NODE
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}
TRANSITION_LIST("Z")
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NODE
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DISPLAY_LINE
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TREE_LEVEL = 0;
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TIME_BAR
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;

784
mux_8x16.bdf Normal file
View file

@ -0,0 +1,784 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
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)
(pin
(input)
(rect 104 448 272 464)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "in5[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 104 536 272 552)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "in6[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 104 568 272 584)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "in7[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 872 192 1048 208)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "result[15..0]" (rect 90 0 149 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 312 272 424 360)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst5" (rect 3 77 25 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 424 272 448 288))
)
(symbol
(rect 312 392 424 480)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst6" (rect 3 77 25 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 424 392 448 408))
)
(symbol
(rect 312 512 424 600)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst7" (rect 3 77 25 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 424 512 448 528))
)
(symbol
(rect 528 152 640 240)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst8" (rect 3 77 25 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 640 152 664 168))
)
(symbol
(rect 528 272 640 360)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst9" (rect 3 77 25 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 640 272 664 288))
)
(symbol
(rect 720 152 832 240)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst10" (rect 3 77 31 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 832 152 856 168))
)
(symbol
(rect 312 152 424 240)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst" (rect 3 77 23 91)(font "Arial" (font_size 8)))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
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(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 424 152 456 176))
)
(connector
(pt 424 200)
(pt 440 200)
(bus)
)
(connector
(pt 456 320)
(pt 424 320)
(bus)
)
(connector
(pt 424 440)
(pt 472 440)
(bus)
)
(connector
(pt 424 560)
(pt 488 560)
(bus)
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(connector
(pt 656 184)
(pt 720 184)
(bus)
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(connector
(pt 440 200)
(pt 440 184)
(bus)
)
(connector
(pt 456 320)
(pt 456 216)
(bus)
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(connector
(pt 656 200)
(pt 640 200)
(bus)
)
(connector
(pt 656 184)
(pt 656 200)
(bus)
)
(connector
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(pt 528 216)
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(connector
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(pt 528 184)
(bus)
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(connector
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(pt 472 304)
(bus)
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(connector
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(pt 488 336)
(bus)
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(connector
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(pt 528 336)
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(connector
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(bus)
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(connector
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(connector
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(connector
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(connector
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(connector
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(connector
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(pt 368 376)
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(connector
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)
(connector
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(connector
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(connector
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(connector
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(connector
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(connector
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(connector
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(connector
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(connector
(pt 832 200)
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(junction (pt 296 496))
(junction (pt 296 376))
(junction (pt 296 256))
(junction (pt 512 256))

113
mux_8x16.bsf Normal file
View file

@ -0,0 +1,113 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 200 240)
(text "mux_8x16" (rect 5 0 67 19)(font "Intel Clear" (font_size 8)))
(text "inst" (rect 8 203 24 220)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "s0" (rect 0 0 14 19)(font "Intel Clear" (font_size 8)))
(text "s0" (rect 21 27 35 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "s1" (rect 0 0 14 19)(font "Intel Clear" (font_size 8)))
(text "s1" (rect 21 43 35 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "s2" (rect 0 0 14 19)(font "Intel Clear" (font_size 8)))
(text "s2" (rect 21 59 35 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "in0[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in0[15..0]" (rect 21 75 78 94)(font "Intel Clear" (font_size 8)))
(line (pt 0 80)(pt 16 80)(line_width 3))
)
(port
(pt 0 96)
(input)
(text "in1[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in1[15..0]" (rect 21 91 78 110)(font "Intel Clear" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "in2[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in2[15..0]" (rect 21 107 78 126)(font "Intel Clear" (font_size 8)))
(line (pt 0 112)(pt 16 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "in3[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in3[15..0]" (rect 21 123 78 142)(font "Intel Clear" (font_size 8)))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 0 144)
(input)
(text "in4[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in4[15..0]" (rect 21 139 78 158)(font "Intel Clear" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 3))
)
(port
(pt 0 160)
(input)
(text "in5[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in5[15..0]" (rect 21 155 78 174)(font "Intel Clear" (font_size 8)))
(line (pt 0 160)(pt 16 160)(line_width 3))
)
(port
(pt 0 176)
(input)
(text "in6[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in6[15..0]" (rect 21 171 78 190)(font "Intel Clear" (font_size 8)))
(line (pt 0 176)(pt 16 176)(line_width 3))
)
(port
(pt 0 192)
(input)
(text "in7[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in7[15..0]" (rect 21 187 78 206)(font "Intel Clear" (font_size 8)))
(line (pt 0 192)(pt 16 192)(line_width 3))
)
(port
(pt 184 32)
(output)
(text "result[15..0]" (rect 0 0 71 19)(font "Intel Clear" (font_size 8)))
(text "result[15..0]" (rect 92 27 163 46)(font "Intel Clear" (font_size 8)))
(line (pt 184 32)(pt 168 32)(line_width 3))
)
(drawing
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
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