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Kacper 2020-06-14 15:38:43 +01:00
parent f169dd46e2
commit 65ec0a4a41
19 changed files with 399 additions and 1352 deletions
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2
ALU_top.bdf
View file

@ -263,7 +263,7 @@ refer to the applicable agreement for further details.
(output) (output)
(rect 800 336 976 352) (rect 800 336 976 352)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "memaddr[10..0]" (rect 90 0 165 17)(font "Intel Clear" )) (text "memaddr[10..0]" (rect 90 0 167 12)(font "Arial" ))
(pt 0 8) (pt 0 8)
(drawing (drawing
(line (pt 0 8)(pt 52 8)) (line (pt 0 8)(pt 52 8))

18
ALU_top.bsf
View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2019 Intel Corporation. All rights reserved. Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at refer to the applicable agreement for further details.
https://fpgasoftware.intel.com/eula.
*/ */
(header "symbol" (version "1.2")) (header "symbol" (version "1.2"))
(symbol (symbol
@ -76,16 +75,9 @@ https://fpgasoftware.intel.com/eula.
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(port (port
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18
CPUProject.bdf
View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2019 Intel Corporation. All rights reserved. Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at refer to the applicable agreement for further details.
https://fpgasoftware.intel.com/eula.
*/ */
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@ -1465,16 +1464,9 @@ https://fpgasoftware.intel.com/eula.
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7
CPUProject.qsf
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@ -62,11 +62,12 @@ set_global_assignment -name POWER_USE_PVA ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VERILOG_FILE max_min.v
set_global_assignment -name VERILOG_FILE LIFOstack.v set_global_assignment -name VERILOG_FILE LIFOstack.v
set_global_assignment -name VERILOG_FILE alu.v set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name MIF_FILE LUTSquares.mif set_global_assignment -name MIF_FILE LUTSquares.mif
set_global_assignment -name BDF_FILE mul8.bdf set_global_assignment -name BDF_FILE mul8.bdf
set_global_assignment -name BDF_FILE abs.bdf
set_global_assignment -name BDF_FILE CPUProject.bdf set_global_assignment -name BDF_FILE CPUProject.bdf
set_global_assignment -name BDF_FILE reg_file.bdf set_global_assignment -name BDF_FILE reg_file.bdf
set_global_assignment -name QIP_FILE ram_data.qip set_global_assignment -name QIP_FILE ram_data.qip
@ -76,12 +77,8 @@ set_global_assignment -name MIF_FILE data.mif
set_global_assignment -name MIF_FILE instr.mif set_global_assignment -name MIF_FILE instr.mif
set_global_assignment -name BDF_FILE mul16.bdf set_global_assignment -name BDF_FILE mul16.bdf
set_global_assignment -name QIP_FILE LUT.qip set_global_assignment -name QIP_FILE LUT.qip
set_global_assignment -name VERILOG_FILE min.v
set_global_assignment -name VERILOG_FILE SM.v set_global_assignment -name VERILOG_FILE SM.v
set_global_assignment -name BDF_FILE ALU_top.bdf set_global_assignment -name BDF_FILE ALU_top.bdf
set_global_assignment -name VERILOG_FILE mux_8x16.v set_global_assignment -name VERILOG_FILE mux_8x16.v
set_global_assignment -name VERILOG_FILE mux_3x16.v
set_global_assignment -name VERILOG_FILE ADD_1.v set_global_assignment -name VERILOG_FILE ADD_1.v
set_global_assignment -name VERILOG_FILE SM_pipelined.v set_global_assignment -name VERILOG_FILE SM_pipelined.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
CPUProject.qws Normal file
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769
abs.bdf
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@ -1,769 +0,0 @@
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WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
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/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
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44
abs.bsf
View file

@ -1,44 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 168 112)
(text "abs" (rect 5 0 26 19)(font "Intel Clear" (font_size 8)))
(text "inst" (rect 8 75 24 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "N[7..0]" (rect 0 0 40 19)(font "Intel Clear" (font_size 8)))
(text "N[7..0]" (rect 21 27 61 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
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(text "ABS[7..0]" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
(text "ABS[7..0]" (rect 76 27 131 46)(font "Intel Clear" (font_size 8)))
(line (pt 152 32)(pt 136 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 136 80))
)
)

41
mux_3x16.bsf → max_min.bsf
View file

@ -20,45 +20,38 @@ refer to the applicable agreement for further details.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
(symbol (symbol
(rect 16 16 200 128) (rect 16 16 200 96)
(text "mux_3x16" (rect 5 0 46 12)(font "Arial" )) (text "max_min" (rect 5 0 42 12)(font "Arial" ))
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11
max_min.v Normal file
View file

@ -0,0 +1,11 @@
module max_min(a, b, maximum, minimum);
input unsigned [7:0] a;
input unsigned [7:0] b;
output unsigned [7:0] maximum;
output unsigned [7:0] minimum;
assign minimum = (a<b) ? a:b;
assign maximum = (a>b) ? a:b;
endmodule

11
max_min.v.bak Normal file
View file

@ -0,0 +1,11 @@
module min_max(a, b, minimum, maximum);
input unsigned [7..0] a;
input unsigned [7..0] b;
output unsigned [7..0] minimum;
output unsigned [7..0] maximum;
assign minimum = (a<b) ? a:b;
assign maximum = (a>b) ? a:b;
endmodule

58
min.bsf
View file

@ -1,58 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
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(text "min" (rect 5 0 19 12)(font "Arial" ))
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(drawing
(rectangle (rect 16 16 144 96)(line_width 1))
)
)

7
min.v
View file

@ -1,7 +0,0 @@
module min(sign, a, b, num);
input sign;
input [7:0] a;
input [7:0] b;
output [7:0] num;
assign num = sign ? a[7:0]:b[7:0];
endmodule

12
min.v.bak
View file

@ -1,12 +0,0 @@
module MIN(
input sign,
input a[7..0],
input b[7..0],
output [7..0] num;
);
assign num = sign ? a[7..0]:b[7..0]
endmodule

351
mul16.bdf
View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2019 Intel Corporation. All rights reserved. Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at refer to the applicable agreement for further details.
https://fpgasoftware.intel.com/eula.
*/ */
(header "graphic" (version "1.4")) (header "graphic" (version "1.4"))
(pin (pin
@ -507,150 +506,6 @@ https://fpgasoftware.intel.com/eula.
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@ -668,6 +523,150 @@ https://fpgasoftware.intel.com/eula.
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@ -716,30 +715,6 @@ https://fpgasoftware.intel.com/eula.
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7
mul16.bsf
View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2019 Intel Corporation. All rights reserved. Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at refer to the applicable agreement for further details.
https://fpgasoftware.intel.com/eula.
*/ */
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331
mul8.bdf
View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2019 Intel Corporation. All rights reserved. Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,42 +16,9 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at refer to the applicable agreement for further details.
https://fpgasoftware.intel.com/eula.
*/ */
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25
mul8.bsf
View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2019 Intel Corporation. All rights reserved. Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,12 +16,11 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at refer to the applicable agreement for further details.
https://fpgasoftware.intel.com/eula.
*/ */
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(input) (input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8))) (text "NUM1[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8))) (text "NUM1[7..0]" (rect 21 43 89 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3)) (line (pt 0 48)(pt 16 48)(line_width 3))
) )
(port (port
(pt 0 64) (pt 0 64)
(input) (input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8))) (text "NUM2[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8))) (text "NUM2[7..0]" (rect 21 59 89 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3)) (line (pt 0 64)(pt 16 64)(line_width 3))
) )
(port (port
(pt 168 32) (pt 200 32)
(output) (output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8))) (text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8))) (text "PROD[15..0]" (rect 105 27 179 46)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32)(line_width 3)) (line (pt 200 32)(pt 184 32)(line_width 3))
) )
(drawing (drawing
(rectangle (rect 16 16 152 80)) (rectangle (rect 16 16 184 80))
) )
) )

19
mux_3x16.v
View file

@ -1,19 +0,0 @@
module mux_3x16 (s, in0, in1, in2, result);
input [1:0]s;
input [15:0]in0;
input [15:0]in1;
input [15:0]in2;
output reg [15:0]result;
always @(*) begin
case(s)
2'b00: result = in0;
2'b01: result = in1;
2'b10: result = in2;
default: result = in0;
endcase
end
endmodule

18
mux_3x16.v.bak
View file

@ -1,18 +0,0 @@
module mux_3x16 (s, in0, in1, in2, result);
input [1:0]s;
input [15:0]in0;
input [15:0]in1;
input [15:0]in2;
output reg [15:0]result;
always @(*) begin
case(s)
2'b00: result = in0;
2'b01: result = in1;
2'b10: result = in2;
endcase
end
endmodule