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CPU completed
This commit is contained in:
Kacper
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commit
4318a5b70b
409
ALU_top.bdf
Normal file
409
ALU_top.bdf
Normal file
|
|
@ -0,0 +1,409 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
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|
||||
92
ALU_top.bsf
Normal file
92
ALU_top.bsf
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
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|
||||
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|
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|
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|
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|
||||
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526
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@ -800,54 +944,6 @@ refer to the applicable agreement for further details.
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|
||||
(text "Rd[15..0]" (rect 21 75 76 94)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "op[5..0]" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "op[5..0]" (rect 21 91 67 110)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "EXEC2" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "EXEC2" (rect 21 107 59 126)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112))
|
||||
)
|
||||
(port
|
||||
(pt 184 32)
|
||||
(output)
|
||||
(text "Rout[15..0]" (rect 0 0 66 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rout[15..0]" (rect 97 27 163 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 184 32)(pt 168 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 184 48)
|
||||
(output)
|
||||
(text "COND" (rect 0 0 36 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "COND" (rect 127 43 163 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 184 48)(pt 168 48))
|
||||
)
|
||||
(port
|
||||
(pt 184 64)
|
||||
(output)
|
||||
(text "CARRY" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CARRY" (rect 122 59 163 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 184 64)(pt 168 64))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 168 144))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 504 416)
|
||||
(pt 632 416)
|
||||
|
|
@ -1299,28 +1466,6 @@ refer to the applicable agreement for further details.
|
|||
(pt 464 400)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "Rs2[15..0]" (rect 826 352 873 369)(font "Intel Clear" ))
|
||||
(pt 816 368)
|
||||
(pt 896 368)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "Rd[15..0]" (rect 826 576 868 593)(font "Intel Clear" ))
|
||||
(pt 816 592)
|
||||
(pt 864 592)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 864 592)
|
||||
(pt 864 392)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 896 392)
|
||||
(pt 864 392)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "s3[2]" (rect 474 608 497 625)(font "Intel Clear" ))
|
||||
(pt 632 624)
|
||||
|
|
@ -1366,21 +1511,11 @@ refer to the applicable agreement for further details.
|
|||
(pt 728 16)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "CLK" (rect 514 -72 534 -55)(font "Intel Clear" ))
|
||||
(pt 504 -56)
|
||||
(pt 536 -56)
|
||||
)
|
||||
(connector
|
||||
(pt 488 -72)
|
||||
(pt 536 -72)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "EXEC" (rect 514 -104 539 -87)(font "Intel Clear" ))
|
||||
(pt 504 -88)
|
||||
(pt 536 -88)
|
||||
)
|
||||
(connector
|
||||
(pt 728 -88)
|
||||
(pt 744 -88)
|
||||
|
|
@ -1686,17 +1821,6 @@ refer to the applicable agreement for further details.
|
|||
(pt 256 -16)
|
||||
(pt 216 -16)
|
||||
)
|
||||
(connector
|
||||
(text "Rs1[15..0]" (rect 826 128 873 145)(font "Intel Clear" ))
|
||||
(pt 816 144)
|
||||
(pt 856 144)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 896 344)
|
||||
(pt 856 344)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1168 304)
|
||||
(pt 1160 304)
|
||||
|
|
@ -1738,16 +1862,6 @@ refer to the applicable agreement for further details.
|
|||
(pt 872 224)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 144)
|
||||
(pt 856 192)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 192)
|
||||
(pt 856 344)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1160 192)
|
||||
(pt 1160 304)
|
||||
|
|
@ -1770,12 +1884,6 @@ refer to the applicable agreement for further details.
|
|||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1288 792)
|
||||
(pt 1288 320)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "<<__$DEF_ALIAS361>>" (rect 549 288 661 305)(font "Intel Clear" )(invisible))
|
||||
(pt 432 304)
|
||||
(pt 616 304)
|
||||
(bus)
|
||||
|
|
@ -1825,20 +1933,6 @@ refer to the applicable agreement for further details.
|
|||
(pt 504 192)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1168 336)
|
||||
(pt 1136 336)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1024 504)
|
||||
(pt 1024 488)
|
||||
)
|
||||
(connector
|
||||
(text "COND" (rect 1024 472 1053 489)(font "Intel Clear" ))
|
||||
(pt 1024 488)
|
||||
(pt 1048 488)
|
||||
)
|
||||
(connector
|
||||
(text "FETCH" (rect 418 32 449 49)(font "Intel Clear" ))
|
||||
(pt 408 48)
|
||||
|
|
@ -1994,6 +2088,159 @@ refer to the applicable agreement for further details.
|
|||
(pt 1176 120)
|
||||
(pt 1224 120)
|
||||
)
|
||||
(connector
|
||||
(text "Rs1[15..0]" (rect 818 128 865 145)(font "Intel Clear" ))
|
||||
(pt 816 144)
|
||||
(pt 856 144)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "Rd[15..0]" (rect 818 576 860 593)(font "Intel Clear" ))
|
||||
(pt 816 592)
|
||||
(pt 856 592)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1120 336)
|
||||
(pt 1168 336)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "COND" (rect 1122 336 1151 353)(font "Intel Clear" ))
|
||||
(pt 1120 352)
|
||||
(pt 1152 352)
|
||||
)
|
||||
(connector
|
||||
(pt 856 352)
|
||||
(pt 936 352)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 144)
|
||||
(pt 856 192)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 192)
|
||||
(pt 856 352)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "Rs2[15..0]" (rect 816 352 863 369)(font "Intel Clear" ))
|
||||
(pt 816 368)
|
||||
(pt 936 368)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 592)
|
||||
(pt 856 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 384)
|
||||
(pt 936 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "ALU_en" (rect 890 320 927 337)(font "Intel Clear" ))
|
||||
(pt 936 336)
|
||||
(pt 880 336)
|
||||
)
|
||||
(connector
|
||||
(text "EXEC2" (rect 890 400 921 417)(font "Intel Clear" ))
|
||||
(pt 936 416)
|
||||
(pt 880 416)
|
||||
)
|
||||
(connector
|
||||
(text "instr[15..10]" (rect 890 384 945 401)(font "Intel Clear" ))
|
||||
(pt 936 400)
|
||||
(pt 880 400)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "EXEC1" (rect 506 -104 537 -87)(font "Intel Clear" ))
|
||||
(pt 536 -88)
|
||||
(pt 496 -88)
|
||||
)
|
||||
(connector
|
||||
(text "CLK" (rect 506 -72 526 -55)(font "Intel Clear" ))
|
||||
(pt 536 -56)
|
||||
(pt 496 -56)
|
||||
)
|
||||
(connector
|
||||
(text "CARRY" (rect 1122 352 1157 369)(font "Intel Clear" ))
|
||||
(pt 1120 368)
|
||||
(pt 1152 368)
|
||||
)
|
||||
(connector
|
||||
(text "CARRY" (rect 1050 504 1085 521)(font "Intel Clear" ))
|
||||
(pt 1096 520)
|
||||
(pt 1040 520)
|
||||
)
|
||||
(connector
|
||||
(text "Rd[15..0]" (rect 1050 520 1092 537)(font "Intel Clear" ))
|
||||
(pt 1096 536)
|
||||
(pt 1040 536)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "Rs1[15..0]" (rect 1050 536 1097 553)(font "Intel Clear" ))
|
||||
(pt 1096 552)
|
||||
(pt 1040 552)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "Rs2[15..0]" (rect 1050 552 1097 569)(font "Intel Clear" ))
|
||||
(pt 1096 568)
|
||||
(pt 1040 568)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "instr[15..0]" (rect 1048 568 1097 585)(font "Intel Clear" ))
|
||||
(pt 1096 584)
|
||||
(pt 1040 584)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "FETCH" (rect 1050 584 1081 601)(font "Intel Clear" ))
|
||||
(pt 1096 600)
|
||||
(pt 1040 600)
|
||||
)
|
||||
(connector
|
||||
(text "EXEC1" (rect 1050 600 1081 617)(font "Intel Clear" ))
|
||||
(pt 1096 616)
|
||||
(pt 1040 616)
|
||||
)
|
||||
(connector
|
||||
(text "EXEC2" (rect 1050 616 1081 633)(font "Intel Clear" ))
|
||||
(pt 1096 632)
|
||||
(pt 1040 632)
|
||||
)
|
||||
(connector
|
||||
(pt 1288 480)
|
||||
(pt 1088 480)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1096 504)
|
||||
(pt 1088 504)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1088 504)
|
||||
(pt 1088 480)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1288 320)
|
||||
(pt 1288 480)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1288 480)
|
||||
(pt 1288 792)
|
||||
(bus)
|
||||
)
|
||||
(junction (pt 504 416))
|
||||
(junction (pt 504 192))
|
||||
(junction (pt 520 432))
|
||||
|
|
@ -2027,3 +2274,4 @@ refer to the applicable agreement for further details.
|
|||
(junction (pt 856 192))
|
||||
(junction (pt 872 -72))
|
||||
(junction (pt 912 -72))
|
||||
(junction (pt 1288 480))
|
||||
|
|
|
|||
|
|
@ -41,14 +41,13 @@ set_global_assignment -name DEVICE AUTO
|
|||
set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name VERILOG_FILE alu.v
|
||||
set_global_assignment -name MIF_FILE LUTSquares.mif
|
||||
set_global_assignment -name BDF_FILE mul8.bdf
|
||||
|
|
@ -65,4 +64,6 @@ set_global_assignment -name BDF_FILE mul16.bdf
|
|||
set_global_assignment -name QIP_FILE LUT.qip
|
||||
set_global_assignment -name VERILOG_FILE min.v
|
||||
set_global_assignment -name VERILOG_FILE SM.v
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
|
||||
set_global_assignment -name BDF_FILE ALU_top.bdf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
113
alu.bsf
Normal file
113
alu.bsf
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 224 192)
|
||||
(text "alu" (rect 5 0 15 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 160 20 172)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "enable" (rect 0 0 24 12)(font "Arial" ))
|
||||
(text "enable" (rect 21 27 45 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "Rs1[15..0]" (rect 0 0 40 12)(font "Arial" ))
|
||||
(text "Rs1[15..0]" (rect 21 43 61 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "Rs2[15..0]" (rect 0 0 41 12)(font "Arial" ))
|
||||
(text "Rs2[15..0]" (rect 21 59 62 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "Rd[15..0]" (rect 0 0 36 12)(font "Arial" ))
|
||||
(text "Rd[15..0]" (rect 21 75 57 87)(font "Arial" ))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "opcode[5..0]" (rect 0 0 48 12)(font "Arial" ))
|
||||
(text "opcode[5..0]" (rect 21 91 69 103)(font "Arial" ))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "mulresult[31..0]" (rect 0 0 59 12)(font "Arial" ))
|
||||
(text "mulresult[31..0]" (rect 21 107 80 119)(font "Arial" ))
|
||||
(line (pt 0 112)(pt 16 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "exec2" (rect 0 0 23 12)(font "Arial" ))
|
||||
(text "exec2" (rect 21 123 44 135)(font "Arial" ))
|
||||
(line (pt 0 128)(pt 16 128)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 208 32)
|
||||
(output)
|
||||
(text "mul1[15..0]" (rect 0 0 41 12)(font "Arial" ))
|
||||
(text "mul1[15..0]" (rect 146 27 187 39)(font "Arial" ))
|
||||
(line (pt 208 32)(pt 192 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 48)
|
||||
(output)
|
||||
(text "mul2[15..0]" (rect 0 0 42 12)(font "Arial" ))
|
||||
(text "mul2[15..0]" (rect 145 43 187 55)(font "Arial" ))
|
||||
(line (pt 208 48)(pt 192 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 64)
|
||||
(output)
|
||||
(text "Rout[15..0]" (rect 0 0 43 12)(font "Arial" ))
|
||||
(text "Rout[15..0]" (rect 144 59 187 71)(font "Arial" ))
|
||||
(line (pt 208 64)(pt 192 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 80)
|
||||
(output)
|
||||
(text "jump" (rect 0 0 18 12)(font "Arial" ))
|
||||
(text "jump" (rect 169 75 187 87)(font "Arial" ))
|
||||
(line (pt 208 80)(pt 192 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 208 96)
|
||||
(output)
|
||||
(text "carry" (rect 0 0 22 12)(font "Arial" ))
|
||||
(text "carry" (rect 165 91 187 103)(font "Arial" ))
|
||||
(line (pt 208 96)(pt 192 96)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 192 160)(line_width 1))
|
||||
)
|
||||
)
|
||||
4
alu.v
4
alu.v
|
|
@ -1,4 +1,4 @@
|
|||
module alu (enable, Rd, Rs1, Rs2, opcode, mulresult, exec2, mul1, mul2, Rout, jump, carry);
|
||||
module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, mul1, mul2, Rout, jump, carry);
|
||||
|
||||
input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
|
||||
input signed [15:0] Rd; // input destination register
|
||||
|
|
@ -76,7 +76,7 @@ always @(*)
|
|||
end
|
||||
6'b011001: begin
|
||||
alusum = {1'b0, Rs1} - {1'b0, Rs2} + carry - {17'b00000000000000001}; // SBC Subtract w/ Carry (Rd = Rs1 - Rs2 + C - 1)
|
||||
carry = slusum[16];
|
||||
carry = alusum[16];
|
||||
end
|
||||
6'b011010: begin
|
||||
alusum = {1'b0, Rs1} - {17'b00000000000000001}; // SBO Subtract 1 (Rd = Rd - 1)
|
||||
|
|
|
|||
57
mul16.bsf
Normal file
57
mul16.bsf
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 216 112)
|
||||
(text "mul16" (rect 5 0 43 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "inst" (rect 8 75 24 92)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "A[15..0]" (rect 0 0 47 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "A[15..0]" (rect 21 43 68 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "B[15..0]" (rect 0 0 47 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "B[15..0]" (rect 21 59 68 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 200 32)
|
||||
(output)
|
||||
(text "PRODUCT[31..0]" (rect 0 0 100 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "PRODUCT[31..0]" (rect 79 27 179 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 200 32)(pt 184 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 184 80))
|
||||
)
|
||||
)
|
||||
Loading…
Reference in a new issue