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(pt 1168 -88) (pt 1128 -88) ) -(connector - (text "SM_rst" (rect 226 64 259 81)(font "Intel Clear" )) - (pt 224 80) - (pt 256 80) -) -(connector - (pt 464 144) - (pt 208 144) - (bus) -) (connector (text "CLK" (rect 578 88 598 105)(font "Intel Clear" )) (pt 568 104) @@ -2570,26 +2522,6 @@ refer to the applicable agreement for further details. (pt 560 120) (pt 600 120) ) -(connector - (pt 600 56) - (pt 568 56) - (bus) -) -(connector - (pt 568 56) - (pt 568 8) - (bus) -) -(connector - (pt 568 8) - (pt 208 8) - (bus) -) -(connector - (pt 208 144) - (pt 208 8) - (bus) -) (connector (pt 872 24) (pt 872 224) @@ -2753,6 +2685,62 @@ refer to the applicable agreement for further details. (pt 1440 344) (bus) ) +(connector + (pt 464 192) + (pt 464 400) + (bus) +) +(connector + (pt 600 56) + (pt 536 56) + (bus) +) +(connector + (text "PC[10..0]" (rect 512 137 529 180)(font "Intel Clear" )(vertical)) + (pt 536 192) + (pt 536 56) + (bus) +) +(connector + (pt 464 192) + (pt 536 192) + (bus) +) +(connector + (pt 536 192) + (pt 632 192) + (bus) +) +(connector + (text "FETCH" (rect 466 40 497 57)(font "Intel Clear" )) + (pt 456 56) + (pt 496 56) +) +(connector + (text "EXEC2" (rect 466 72 497 89)(font "Intel Clear" )) + (pt 456 88) + (pt 496 88) +) +(connector + (text "EXEC1" (rect 466 56 497 73)(font "Intel Clear" )) + (pt 456 72) + (pt 496 72) +) +(connector + (text "CLK" (rect 284 40 304 57)(font "Intel Clear" )) + (pt 272 56) + (pt 304 56) +) +(connector + (text "E2" (rect 282 56 293 73)(font "Intel Clear" )) + (pt 272 72) + (pt 304 72) +) +(connector + (text "SM_rst" (rect 274 72 307 89)(font "Intel Clear" )) + (pt 272 88) + (pt 304 88) +) (junction (pt 856 192)) (junction (pt 136 320)) (junction (pt 136 352)) @@ -2779,3 +2767,4 @@ refer to the applicable agreement for further details. (junction (pt 576 512)) (junction (pt 1416 496)) (junction (pt 872 24)) +(junction (pt 536 192)) diff --git a/CPUProject.qsf b/CPUProject.qsf index 7cf496f..28084ff 100644 --- a/CPUProject.qsf +++ b/CPUProject.qsf @@ -48,6 +48,7 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name VERILOG_FILE LIFOstack.v set_global_assignment -name VERILOG_FILE alu.v set_global_assignment -name MIF_FILE LUTSquares.mif @@ -66,5 +67,4 @@ set_global_assignment -name VERILOG_FILE min.v set_global_assignment -name VERILOG_FILE SM.v set_global_assignment -name BDF_FILE ALU_top.bdf set_global_assignment -name VERILOG_FILE mux_8x16.v -set_global_assignment -name VERILOG_FILE mux_3x16.v -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name VERILOG_FILE mux_3x16.v \ No newline at end of file diff --git a/CPUProject.qws b/CPUProject.qws index fd250b3..adffd16 100644 Binary files a/CPUProject.qws and b/CPUProject.qws differ diff --git a/DECODE.v b/DECODE.v index 02715b7..6717c52 100644 --- a/DECODE.v +++ b/DECODE.v @@ -50,33 +50,33 @@ module DECODE wire NOP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0]; wire STP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & op[0]; - assign R0_count = EXEC1 & (~(UJMP | (JMP & ~COND_result) | STP)); - assign R0_en = (EXEC1 & (~(STORE | NOP | STP | LOAD) & ~Rd[2] & ~Rd[1] & ~Rd[0] | UJMP | JMP & COND_result)) | (EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & ~Rd[0]); - assign R1_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & Rd[0]); - assign R2_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LOAD & ~Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & Rd[1] & ~Rd[0]); - assign R3_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LOAD & ~Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & Rd[1] & Rd[0]); - assign R4_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LOAD & Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & ~Rd[0]); - assign R5_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LOAD & Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & Rd[0]); - assign R6_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LOAD & Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & ~Rd[0]); - assign R7_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LOAD & Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & Rd[0]); - assign s1[2] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[2]) | (STORE & Rls[2]) | (PSH & Rs1[2]); - assign s1[1] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[1]) | (STORE & Rls[1]) | (PSH & Rs1[1]); - assign s1[0] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[0]) | (STORE & Rls[0]) | (PSH & Rs1[0]); - assign s2[2] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[2]); - assign s2[1] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[1]); - assign s2[0] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[0]); - assign s3[2] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rd[2]); - assign s3[1] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rd[1]); - assign s3[0] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rd[0]); + assign R0_count = EXEC1 & (~(UJMP | (JMP & COND_result) | STP)); + assign R0_en = (EXEC1 & (~(STORE | NOP | STP | LOAD | PSH) & ~Rd[2] & ~Rd[1] & ~Rd[0] | UJMP | JMP & COND_result)) | (EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & ~Rd[0]); + assign R1_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & Rd[0]); + assign R2_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LOAD & ~Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & Rd[1] & ~Rd[0]); + assign R3_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LOAD & ~Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & Rd[1] & Rd[0]); + assign R4_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) & Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LOAD & Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & ~Rd[0]); + assign R5_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) & Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LOAD & Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & Rd[0]); + assign R6_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) & Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LOAD & Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & ~Rd[0]); + assign R7_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP | PSH) & Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LOAD & Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & Rd[0]); + assign s1[2] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[2]) | (STORE & Rls[2]) | (PSH & Rs1[2]); + assign s1[1] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[1]) | (STORE & Rls[1]) | (PSH & Rs1[1]); + assign s1[0] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[0]) | (STORE & Rls[0]) | (PSH & Rs1[0]); + assign s2[2] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[2]); + assign s2[1] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[1]); + assign s2[0] = (~(UJMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[0]); + assign s3[2] = (~(STORE | LOAD | NOP | STP | PSH | POP) & Rd[2]); + assign s3[1] = (~(STORE | LOAD | NOP | STP | PSH | POP) & Rd[1]); + assign s3[0] = (~(STORE | LOAD | NOP | STP | PSH | POP) & Rd[0]); assign s4 = ~LOAD; assign RAMd_wren = EXEC1 & STORE; assign RAMd_en = EXEC1 & (STORE | LOAD); assign RAMi_en = FETCH; assign ALU_en = LOAD | STORE; assign E2 = EXEC1 & (LOAD | MUL | MLA | MLS | POP); - assign stack_en = (EXEC1 & PSH) | POP; + assign stack_en = (EXEC1 & PSH) | ((EXEC1 | EXEC2) & POP); assign stack_rst = STP; - assign stack_rw = POP; + assign stack_rw = EXEC1 & PSH; endmodule \ No newline at end of file diff --git a/SM.v b/SM.v index 09753b3..d81d32f 100644 --- a/SM.v +++ b/SM.v @@ -2,7 +2,7 @@ module SM ( input CLK, input E2, - input RST, + input RST, //resets state machine to FETCH output FETCH, output EXEC1, output EXEC2 @@ -12,12 +12,30 @@ reg [2:0]s = 3'b1; //current state initialised to 001 always @(posedge CLK) //Change on rising edge of clock begin - s[2] <= ~s[2] & s[1] & ~s[0] & E2 & ~RST; - s[1] <= ~s[2] & ~s[1] & s[0] & ~RST; - s[0] <= (~s[2] & s[1] & ~s[0] & ~E2) | (s[2] & ~s[1] & ~s[0]) | RST; - end + case(s) + 3'b000: s = 3'b001; //if in 000, go to FETCH + 3'b001: begin + if(!RST) + s = 3'b010; + else + s = 3'b001; + end + 3'b010: begin //if in EXEC1, go to EXEC2 if E2=1 or FETCH if E2=0 + if(!RST) + if(E2) + s = 3'b100; + else + s = 3'b001; + else + s = 3'b001; + end + 3'b100: s = 3'b001; //if in EXEC2, go to FETCH + default: s = 3'b001; + endcase +end assign FETCH = s[0]; assign EXEC1 = s[1]; assign EXEC2 = s[2]; + endmodule diff --git a/data.mif b/data.mif index 32d8d9a..ec54421 100644 --- a/data.mif +++ b/data.mif @@ -27,16 +27,17 @@ CONTENT BEGIN 003 : FFFF; 004 : BFFF; 005 : 000A; - 006 : 001B; - 007 : 001E; - 008 : 0021; - 009 : 0024; - 00A : 0027; + 006 : 0017; + 007 : 001A; + 008 : 001D; + 009 : 0020; + 00A : 0024; 00B : 0000; - 00C : 002B; - 00D : 002E; - 00E : 0031; - 00F : 0036; + 00C : 0027; + 00D : 002A; + 00E : 002D; + 00F : 0032; 010 : AAAA; - [011..7FF] : 0000; + 011 : 0004; + [013..7FF] : 0000; END; diff --git a/instr.mif b/instr.mif index d4f2f08..419e57c 100644 --- a/instr.mif +++ b/instr.mif @@ -28,62 +28,58 @@ CONTENT BEGIN 4 : 2D20; 5 : 3161; 6 : 3448; - 7 : 3993; - 8 : 3AA5; - 9 : D003; - 10 : 3CE2; - 11 : A003; - 12 : 9804; - 13 : 38A5; - 14 : 3FC0; - 15 : 419F; - 16 : 304F; - 17 : 5008; - 18 : 5028; - 19 : 284F; - 20 : 43F7; - 21 : 3568; - 22 : 47F5; - 23 : 484D; - 24 : 8806; - 25 : 0040; - 26 : B800; - 27 : 8807; - 28 : 085A; - 29 : B800; - 30 : 8808; - 31 : 0A7D; - 32 : B800; - 33 : 8809; - 34 : 0C53; - 35 : B801; - 36 : 880A; - 37 : B00B; - 38 : 0E70; - 39 : B800; - 40 : 880C; - 41 : 1063; - 42 : B800; - 43 : 880D; - 44 : 126D; - 45 : B800; - 46 : 880E; - 47 : 147A; - 48 : B800; - 49 : 880F; - 50 : 5340; - 51 : 53C0; - 52 : 1678; - 53 : B800; - 54 : 1863; - 55 : 1A5A; - 56 : 1FB8; - 57 : 7C00; - 58 : 1C77; - 59 : 204C; - 60 : A810; - 61 : 226D; - 62 : 246D; - 63 : 7E00; - [64..2047] : 0000; + 7 : D002; + 8 : B002; + 9 : 9804; + 10 : B811; + 11 : 419F; + 12 : 304F; + 13 : 5008; + 14 : 5028; + 15 : 284F; + 16 : 43F7; + 17 : 3568; + 18 : 45F5; + 19 : 484D; + 20 : 8806; + 21 : 0040; + 22 : B800; + 23 : 8807; + 24 : 085A; + 25 : B800; + 26 : 8808; + 27 : 0A6F; + 28 : B800; + 29 : 8809; + 30 : 0C53; + 31 : B801; + 32 : 880A; + 33 : B00B; + 34 : 0E70; + 35 : B800; + 36 : 880C; + 37 : 1063; + 38 : B800; + 39 : 880D; + 40 : 126D; + 41 : B800; + 42 : 880E; + 43 : 147E; + 44 : B800; + 45 : 880F; + 46 : 5340; + 47 : 53C0; + 48 : 1678; + 49 : B800; + 50 : 1863; + 51 : 1A5F; + 52 : 1FB8; + 53 : 7C00; + 54 : 1C77; + 55 : 204C; + 56 : A810; + 57 : 226D; + 58 : 246D; + 59 : 7E00; + [60..2047] : 0000; END;