supleed2/ELEC40006-P1-CW
1
0
Fork 0
mirror of https://github.com/supleed2/ELEC40006-P1-CW.git synced 2024-12-22 21:45:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

ALU enable control added, minor fix with RRC

Browse source 
Multiply still to be updated
This commit is contained in:
Aadi Desai 2020-06-02 16:57:58 +01:00
parent 3f0c91b0ff
commit 2ca1e90a2c
1 changed files with 77 additions and 70 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
alu.v
View file

@ -35,6 +35,8 @@ assign JC7 = (Rs1 != Rs2);
assign JC8 = (Rs1 < 0);
always @(*)
begin
if(!enable)
begin
case (opcode)
6'b000000: alusum = {1'b1, Rd}; // JMP Unconditional Jump, first bit high to indicate jump and passes through Rd
@ -97,7 +99,7 @@ always @(*)
6'b100011: ;
6'b100100: alusum = {1'b0, (Rs1 >> Rs2[3:0]) | (Rs1 << (16 - Rs2[3:0]))}; // ROR Shift Right Loop (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Rs1[15])
6'b100101: alusum = ({Rs1, carryin} >> Rs2[3:0]) | ({Rs1, carryin} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
6'b100101: alusum = ({Rs1, carryin} >> (Rs2 % 17)) | ({Rs1, carryin} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
6'b100110: ;
6'b100111: ;
@ -107,6 +109,11 @@ always @(*)
default: ; // During Load & Store as well as undefined opcodes
endcase;
end
else
begin
alusum = {1'b0, 16'h0000}; // Bring output low during Load/Store so it does not interfere
end
end
/*
always @(*)