ALU enable control added, minor fix with RRC

Multiply still to be updated

alu.v

@@ -35,6 +35,8 @@ assign JC7 = (Rs1 != Rs2);
 assign JC8 = (Rs1 < 0);
 
 always @(*)
+	begin
+		if(!enable)
 			begin
 			case (opcode)
 				6'b000000: alusum = {1'b1, Rd}; // JMP Unconditional Jump, first bit high to indicate jump and passes through Rd
@@ -97,7 +99,7 @@ always @(*)
 				6'b100011: ;
 				
 				6'b100100: alusum = {1'b0, (Rs1 >> Rs2[3:0]) | (Rs1 << (16 - Rs2[3:0]))}; // ROR Shift Right Loop (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Rs1[15])
-			6'b100101: alusum = ({Rs1, carryin} >> Rs2[3:0]) | ({Rs1, carryin} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
+				6'b100101: alusum = ({Rs1, carryin} >> (Rs2 % 17)) | ({Rs1, carryin} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
 				6'b100110: ;
 				6'b100111: ;
 				
@@ -107,6 +109,11 @@ always @(*)
 				default: ; // During Load & Store as well as undefined opcodes
 			endcase;
 			end
+		else
+			begin
+				alusum = {1'b0, 16'h0000}; // Bring output low during Load/Store so it does not interfere
+			end
+	end
 
 /*	
 always @(*)