From 20f2adc4a14e0c7e3205ccd5dbc00e152727a0e5 Mon Sep 17 00:00:00 2001 From: Kacper Date: Tue, 9 Jun 2020 19:01:55 +0100 Subject: [PATCH] Removed some waveform and test files --- CPUProject.qsf | 44 ++++++++++++++++++++------------------------ CPUProject.qws | Bin 0 -> 48 bytes 2 files changed, 20 insertions(+), 24 deletions(-) create mode 100644 CPUProject.qws diff --git a/CPUProject.qsf b/CPUProject.qsf index 82edde9..f889818 100644 --- a/CPUProject.qsf +++ b/CPUProject.qsf @@ -38,13 +38,31 @@ set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE AUTO -set_global_assignment -name TOP_LEVEL_ENTITY SM_pipelined +set_global_assignment -name TOP_LEVEL_ENTITY CPUProject set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020" set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name POWER_USE_INPUT_FILES OFF +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS OFF -section_id eda_simulation +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING OFF -section_id eda_simulation +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME ADD_1 -section_id eda_simulation +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" +set_global_assignment -name POWER_USE_PVA ON +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name VERILOG_FILE LIFOstack.v set_global_assignment -name VERILOG_FILE alu.v set_global_assignment -name MIF_FILE LUTSquares.mif @@ -65,26 +83,4 @@ set_global_assignment -name BDF_FILE ALU_top.bdf set_global_assignment -name VERILOG_FILE mux_8x16.v set_global_assignment -name VERILOG_FILE mux_3x16.v set_global_assignment -name VERILOG_FILE ADD_1.v -set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf -set_global_assignment -name POWER_USE_INPUT_FILES ON -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" -set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation -set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan -set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation -set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulation -set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation -set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME ADD_1 -section_id eda_simulation -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" -set_global_assignment -name POWER_USE_PVA ON -set_global_assignment -name VERILOG_FILE SM_pipelined.v -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name POWER_INPUT_FILE_NAME simulation/qsim/CPUProject.msim.vcd -section_id cpuproject.msim.vcd -set_instance_assignment -name POWER_READ_INPUT_FILE cpuproject.msim.vcd -to ADD_1 -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name VERILOG_FILE SM_pipelined.v \ No newline at end of file diff --git a/CPUProject.qws b/CPUProject.qws new file mode 100644 index 0000000000000000000000000000000000000000..63563b76eda4b19c3f4f321afd3f1b7df67b8d5e GIT binary patch literal 48 ocmZ?JV1NM`h8%`OhGK>ihIoc@hJ1!1hHN0O04SEskP1@-0GYrBX8-^I literal 0 HcmV?d00001