mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
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86 lines
2.6 KiB
Plaintext
86 lines
2.6 KiB
Plaintext
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 200 160)
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(text "LIFOstack" (rect 5 0 47 12)(font "Arial" ))
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(text "inst" (rect 8 128 20 140)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "Din[15..0]" (rect 0 0 36 12)(font "Arial" ))
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(text "Din[15..0]" (rect 21 27 57 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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(port
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(pt 0 48)
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(input)
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(text "clk" (rect 0 0 10 12)(font "Arial" ))
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(text "clk" (rect 21 43 31 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 1))
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)
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(port
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(pt 0 64)
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(input)
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(text "en" (rect 0 0 9 12)(font "Arial" ))
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(text "en" (rect 21 59 30 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 1))
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)
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(port
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(pt 0 80)
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(input)
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(text "rst" (rect 0 0 10 12)(font "Arial" ))
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(text "rst" (rect 21 75 31 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80)(line_width 1))
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)
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(port
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(pt 0 96)
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(input)
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(text "rw" (rect 0 0 9 12)(font "Arial" ))
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(text "rw" (rect 21 91 30 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96)(line_width 1))
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)
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(port
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(pt 184 32)
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(output)
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(text "Dout[15..0]" (rect 0 0 42 12)(font "Arial" ))
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(text "Dout[15..0]" (rect 121 27 163 39)(font "Arial" ))
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(line (pt 184 32)(pt 168 32)(line_width 3))
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)
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(port
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(pt 184 48)
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(output)
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(text "empty" (rect 0 0 25 12)(font "Arial" ))
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(text "empty" (rect 138 43 163 55)(font "Arial" ))
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(line (pt 184 48)(pt 168 48)(line_width 1))
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)
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(port
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(pt 184 64)
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(output)
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(text "full" (rect 0 0 10 12)(font "Arial" ))
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(text "full" (rect 153 59 163 71)(font "Arial" ))
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(line (pt 184 64)(pt 168 64)(line_width 1))
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)
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(drawing
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(rectangle (rect 16 16 168 128)(line_width 1))
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)
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)
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