mirror of
https://github.com/supleed2/EIE4-FYP.git
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140 lines
4.8 KiB
Systemverilog
140 lines
4.8 KiB
Systemverilog
`default_nettype none
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module can
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( input var i_clk
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, input var i_rst_n
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, input var [10:0] i_id
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, input var [10:0] i_mask
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, input var i_rx
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, output var o_tx
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, output var [10:0] o_id
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, output var [ 7:0] o_data0
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, output var [ 7:0] o_data1
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, output var [ 7:0] o_data2
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, output var [ 7:0] o_data3
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, output var [ 7:0] o_data4
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, output var [ 7:0] o_data5
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, output var [ 7:0] o_data6
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, output var [ 7:0] o_data7
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, output var o_pulse
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);
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logic rx;
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always_ff @(posedge i_clk) // Capture i_rx on rising edge of i_clk
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rx <= i_rx;
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logic rx_p;
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always_ff @(posedge i_clk) // Store previous value of i_rx
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rx_p <= rx;
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logic rx_r;
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always_comb rx_r = rx && !rx_p; // Detect rising edge of rx
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logic [8:0] div_1m;
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always_ff @(posedge i_clk)
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if (!i_rst_n) div_1m <= 9'd0; // Reset
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else if (rx_r) div_1m <= 9'd1; // Align to 1 -> 0 transition
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else if (div_1m == 9'd383) div_1m <= 9'd0; // Wrap at 384
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else div_1m <= div_1m + 1; // Increment
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logic bit_t_75;
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always_ff @(posedge i_clk) bit_t_75 <= (div_1m == 9'd287); // 75% of bit time
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logic eof;
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logic stuff_bit;
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logic [2:0] stuff_count;
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logic [98:0] rx_shift;
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always_ff @(posedge i_clk) // Store incoming bits in a shift register
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if (!i_rst_n || eof) rx_shift <= '1; // Reset or End-of-Frame
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else if (bit_t_75 && !stuff_bit) rx_shift <= {rx_shift[97:0], rx};
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// Shift in next bit at 75% of bit time if not a stuff bit
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always_comb stuff_bit = (stuff_count == 3'd4); // Detect bit stuffing
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logic rx_prev;
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always_ff @(posedge i_clk) if (bit_t_75) rx_prev <= rx;
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always_ff @(posedge i_clk)
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if (!i_rst_n) stuff_count <= 3'd0; // Reset
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else if (bit_t_75 && stuff_bit) stuff_count <= 3'd0; // Stuffed bit
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else if (bit_t_75 && (rx_prev == rx)) stuff_count <= stuff_count + 1; // Same bit, increment count
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else if (bit_t_75) stuff_count <= 3'd0; // Different bit, reset count
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logic [6:0] det_eof;
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always_ff @(posedge i_clk)
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if (!i_rst_n) det_eof <= 7'd0; // Reset
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else if (bit_t_75) det_eof <= {det_eof[5:0], rx}; // Shift in next bit at 75% of bit time
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always_ff @(posedge i_clk) eof <= &{det_eof}; // Detect EOF (7 consecutive recessive/1 bits)
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// Break out rx_shift into individual signals
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logic b_sof;
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logic [10:0] b_id;
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logic b_rtr;
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logic b_ide;
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logic b_r0;
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logic [ 3:0] b_dlc;
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logic [63:0] b_data;
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logic [14:0] b_crc;
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logic b_crc_del;
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always_comb b_sof = rx_shift[98];
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always_comb b_id = rx_shift[97:87];
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always_comb b_rtr = rx_shift[86];
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always_comb b_ide = rx_shift[85];
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always_comb b_r0 = rx_shift[84];
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always_comb b_dlc = rx_shift[83:80];
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always_comb b_data = rx_shift[79:16];
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always_comb b_crc = rx_shift[15:1];
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always_comb b_crc_del = rx_shift[0];
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logic id_match;
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always_ff @(posedge i_clk) id_match <= ((i_id & i_mask) == (b_id & i_mask)); // Check if CAN ID matches
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logic dlc_match;
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always_ff @(posedge i_clk) dlc_match <= (b_dlc == 4'd8); // Check if DLC is 8 (Hardcoded in Stacksynth)
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logic crc_match;
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always_ff @(posedge i_clk) crc_match <= 1'b1; // TODO: Implement CRC checking
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logic msg_valid; // Check if message is valid
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always_ff @(posedge i_clk) msg_valid <= &{id_match, !b_rtr, !b_ide, !b_r0, dlc_match, crc_match, b_crc_del};
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always_ff @(posedge i_clk)
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if (!i_rst_n) o_tx <= 1'b1; // Reset
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else if (div_1m == 9'd1) o_tx <= !msg_valid; // Output dominant (0) if message valid, at start of bit time
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always_ff @(posedge i_clk)
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if (!i_rst_n) o_id <= 11'd0; // Reset
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else if (div_1m == 9'd1 && msg_valid) o_id <= b_id; // Update received ID if valid, at start of bit time
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logic [63:0] data;
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always_ff @(posedge i_clk)
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if (!i_rst_n) data <= 64'd0; // Reset
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else if (div_1m == 9'd1 && msg_valid) data <= b_data; // Update data if valid, at start of bit time
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always_ff @(posedge i_clk)
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if (!i_rst_n) o_pulse <= 1'b0; // Reset
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else if (div_1m == 9'd1) o_pulse <= msg_valid; // Output pulse if message valid, at start of bit time
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else o_pulse <= 1'b0; // Clear pulse after 1 cycle (48MHz)
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// Output data as individual bytes
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always_comb o_data0 = data[63:56];
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always_comb o_data1 = data[55:48];
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always_comb o_data2 = data[47:40];
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always_comb o_data3 = data[39:32];
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always_comb o_data4 = data[31:24];
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always_comb o_data5 = data[23:16];
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always_comb o_data6 = data[15:8];
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always_comb o_data7 = data[7:0];
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endmodule
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/* CRC Formula from BOSCH CAN Specification
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crc_rg = '0; // Initialise shift register
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repeat {
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crcnxt = nxtbit ^ crc_rg[14];
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crc_rg = {crc_rg[13:0], 1'b0}; // Shift left by 1
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if (crcnxt) crc_rg = crc_rg ^ 15'h4599; // XOR with 15'h4599
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} until (input runs out)
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*/
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