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https://github.com/supleed2/EIE4-FYP.git
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61 lines
2.6 KiB
Systemverilog
61 lines
2.6 KiB
Systemverilog
`default_nettype none
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module dacDriver
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( input var i_clk36 // Runs at 36.864MHz (48k * 768)
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, input var i_rst36_n
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, input var i_wait // don't retrieve new packet if high
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, input var [47:0] i_lraudio // Received at 48kHz, capture when o_rdreq high
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, output var o_rdreq // Pulse 1 cycle at 36.864MHz if i_wait low
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, output var o_lrck // Runs at 48kHz (i_clk36 / 768), changes on falling edge of o_bck
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, output var o_bck // Runs at 2.304MHz (48k * 48, i_clk36 / 16)
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, output var o_data // Changes on falling edge of o_bck
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);
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logic [8:0] div_48k;
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always_ff @(posedge i_clk36) // Count half 48kHz cycle
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if (!i_rst36_n) div_48k <= 0;
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else if (div_48k == 9'd384) div_48k <= 0;
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else div_48k <= div_48k + 1;
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logic clk_48k;
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always_ff @(posedge i_clk36) // Generate 48kHz clock
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if (!i_rst36_n) clk_48k <= 0;
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else if (div_48k == 9'd384) clk_48k <= ~clk_48k;
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logic clk_48k_past;
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always_ff @(posedge i_clk36) // Track rising of 48kHz clock
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clk_48k_past <= clk_48k;
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logic [3:0] div_bck;
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always_ff @(posedge i_clk36) // Count half 2.304MHz cycle
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if (!i_rst36_n) div_bck <= 0;
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else if (div_bck == 4'd8) div_bck <= 0;
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else div_bck <= div_bck + 1;
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always_ff @(posedge i_clk36) // Generate 2.304MHz clock
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if (!i_rst36_n) o_bck <= 0;
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else if (div_bck == 4'd8) o_bck <= ~o_bck;
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always_ff @(posedge i_clk36) // Pulse Read Request on rising edge of clk_48k if i_wait low
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if (!i_rst36_n) o_rdreq <= 0;
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else if (!i_wait && clk_48k && !clk_48k_past) o_rdreq <= 1;
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else o_rdreq <= 0;
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logic [47:0] lraudio;
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always_ff @(posedge i_clk36) // Capture new audio sample on Read Request
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if (!i_rst36_n) lraudio <= '0;
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else if (!i_wait && clk_48k && !clk_48k_past) lraudio <= i_lraudio;
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always_ff @(negedge o_bck) // Update LRCK on falling edge of BCK (As in PCM1780 Datasheet)
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if (!i_rst36_n) o_lrck <= 0;
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else o_lrck <= clk_48k;
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logic [23:0] audio_buf;
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always_ff @(negedge o_bck) // Update DATA on falling edge of BCK (As in PCM1780 Datasheet)
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if (!i_rst36_n) {o_data, audio_buf} <= {25{1'b0}}; // Reset to all 0s
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else if (clk_48k && !clk_48k_past) {o_data, audio_buf} <= {lraudio[47:24], 1'b0}; // Load left sample into shifted output
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else if (!clk_48k && clk_48k_past) {o_data, audio_buf} <= {lraudio[23:0], 1'b0}; // Load right sample into shifted output
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else {o_data, audio_buf} <= {audio_buf, 1'b0}; // Shift loaded sample into o_data
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endmodule
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