Aadi Desai bb94e58a53 Completed dacVolume.sv, issues remain ... If dacVolume and testSaw are instantiated in the same design, the design fails to run		2023-05-22 13:28:14 +01:00
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dacDriver.sv	Working version of dac driver	2023-05-16 22:12:41 +01:00
dacVolume.sv	Completed dacVolume.sv, issues remain	2023-05-22 13:28:14 +01:00
flip.sv	Replace assign with always_comb in rtl/	2023-05-18 12:01:56 +01:00
flipPwm.sv	Replace assign with always_comb in rtl/	2023-05-18 12:01:56 +01:00
genSaw.sv	Flip MSB of square wave, avoid DAC automute	2023-05-18 16:19:53 +01:00
pcmfifo.sv	Add pcmfifo SystemVerilog module	2023-03-10 17:47:39 +00:00