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https://github.com/supleed2/EIE4-FYP.git
synced 2024-09-19 21:36:17 +00:00
42 lines
1.2 KiB
Python
42 lines
1.2 KiB
Python
from migen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.doc import ModuleDoc
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# CDC FIFO Module for PCM Data ---------------------------------------------------------------------
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class pcmFifo(Module, AutoCSR, ModuleDoc):
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"""
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DAC Driver Module
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Connect output pins of the DAC
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"""
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def __init__(self, platform, pads):
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self.pads = pads
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self.i_clk48 = Signal()
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self.i_rst48_n = Signal()
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self.i_dvalid = Signal()
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self.i_din = Signal(2)
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self.o_full = Signal()
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self.i_clk36 = Signal()
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self.i_rst36_n = Signal()
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self.i_rdreq = Signal()
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self.o_dout = Signal(2)
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self.o_empty = Signal()
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# # #
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self.specials += Instance("pcmfifo",
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i_i_clk48=self.i_clk48,
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i_i_rst48_n=self.i_rst48_n,
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i_i_dvalid=self.i_dvalid,
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i_i_din=self.i_din,
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o_o_full=self.o_full,
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i_i_clk36=self.i_clk36,
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i_i_rst36_n=self.i_rst36_n,
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i_i_rdreq=self.i_rdreq,
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o_o_dout=self.o_dout,
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o_o_empty=self.o_empty,
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)
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platform.add_source("rtl/pcmfifo.sv")
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