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109 lines
3.8 KiB
Systemverilog
109 lines
3.8 KiB
Systemverilog
////////////////////////////////////////////////////////////////////////////////
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//
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// The Verilog logic in this module is based on the paper by Clifford E.
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// Cummings, of Sunburst Design, Inc, titled: "Simulation and Synthesis
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// Techniques for Asynchronous FIFO Design". This paper may be found at
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// http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf.
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//
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// Minor edits to that logic have been made by Gisselquist Technology, LLC.
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// Gisselquist Technology, LLC, asserts no copywrite or ownership of these
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// minor edits. The edited Verilog file can be found at
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// https://github.com/ZipCPU/website/blob/master/examples/afifo.v, which also
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// contains many properties (Licensed under GPL, found at
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// https://www.gnu.org/licenses/#GPL) for use in Formal Verification. Those
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// properties have been removed in this module.
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//
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////////////////////////////////////////////////////////////////////////////////
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`default_nettype none
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module pcmfifo
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#(parameter int DW = 2
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, parameter int AW = 4
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)(input var i_clk48
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, input var i_rst48_n
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, input var i_dvalid
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, input var [DW-1:0] i_din
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, output var o_full
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// ^ 48MHz Domain, v 36MHz Domain
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, input var i_clk36
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, input var i_rst36_n
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, input var i_rdreq
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, output var [DW-1:0] o_dout
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, output var o_empty
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);
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logic [AW-1:0] w_addr;
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logic w_full_next;
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logic [AW :0] w_ptr;
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logic [AW :0] w_ptr_next;
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logic [AW :0] w_ptr_grey;
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logic [AW :0] w_ptr_grey_buf1;
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logic [AW :0] w_ptr_grey_buf2;
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logic [AW :0] w_ptr_grey_next;
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logic [AW-1:0] r_addr;
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logic r_empty_next;
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logic [AW :0] r_ptr;
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logic [AW :0] r_ptr_next;
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logic [AW :0] r_ptr_grey;
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logic [AW :0] r_ptr_grey_buf1;
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logic [AW :0] r_ptr_grey_buf2;
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logic [AW :0] r_ptr_grey_next;
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logic [DW-1:0] mem [0:((1 << AW)-1)];
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// Cross read Grey pointer to Write Domain (48MHz)
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always_ff @(posedge i_clk48, negedge i_rst48_n)
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if (!i_rst48_n) {r_ptr_grey_buf2, r_ptr_grey_buf1} <= '0;
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else {r_ptr_grey_buf2, r_ptr_grey_buf1} <= {r_ptr_grey_buf1, r_ptr_grey};
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// Calculate next write addr
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assign w_addr = w_ptr[AW-1:0];
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// Calculate next write graycode
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assign w_ptr_next = w_ptr + { {(AW){1'b0}}, ((i_dvalid) && (!o_full)) };
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assign w_ptr_grey_next = (w_ptr_next >> 1) ^ w_ptr_next;
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// Register write addr and write graycode
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always_ff @(posedge i_clk48, negedge i_rst48_n)
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if (!i_rst48_n) {w_ptr, w_ptr_grey} <= 0;
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else {w_ptr, w_ptr_grey} <= {w_ptr_next, w_ptr_grey_next};
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// Update whether fifo is full on next clock
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assign w_full_next = (w_ptr_grey_next == {~r_ptr_grey_buf2[AW:AW-1], r_ptr_grey_buf2[AW-2:0] });
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always_ff @(posedge i_clk48, negedge i_rst48_n)
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if (!i_rst48_n) o_full <= 1'b0;
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else o_full <= w_full_next;
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// Write to FIFO on Write Domain (48MHz) clock
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always_ff @(posedge i_clk48)
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if ((i_dvalid) && (!o_full)) mem[w_addr] <= i_din;
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// Cross write Grey pointer to Read Domain (36MHz)
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always_ff @(posedge i_clk36, negedge i_rst36_n)
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if (!i_rst36_n) {w_ptr_grey_buf2, w_ptr_grey_buf1} <= 0;
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else {w_ptr_grey_buf2, w_ptr_grey_buf1} <= {w_ptr_grey_buf1, w_ptr_grey};
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// Calculate next read address
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assign r_addr = r_ptr[AW-1:0];
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// Calculate next read graycode
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assign r_ptr_next = r_ptr + { {(AW){1'b0}}, ((i_rdreq) && (!o_empty)) };
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assign r_ptr_grey_next = (r_ptr_next >> 1) ^ r_ptr_next;
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// Register read addr and read graycode
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always_ff @(posedge i_clk36, negedge i_rst36_n)
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if (!i_rst36_n) {r_ptr, r_ptr_grey} <= 0;
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else {r_ptr, r_ptr_grey} <= {r_ptr_next, r_ptr_grey_next};
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// Update whether fifo is empty on next clock
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assign r_empty_next = (r_ptr_grey_next == w_ptr_grey_buf2);
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always_ff @(posedge i_clk36, negedge i_rst36_n)
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if (!i_rst36_n) o_empty <= 1'b1;
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else o_empty <= r_empty_next;
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// Output read data combinatorially
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assign o_dout = mem[r_addr];
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endmodule |