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21 lines
364 B
Systemverilog
21 lines
364 B
Systemverilog
`default_nettype none
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module flipPwm
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( input var clk
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, input var [23:0] rgb
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, output var ledr
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, output var ledg
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, output var ledb
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);
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logic [7:0] counter;
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always_ff @(posedge clk)
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counter <= counter + 1;
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assign ledr = (rgb[23:16] > counter);
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assign ledg = (rgb[15: 8] > counter);
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assign ledb = (rgb[ 7: 0] > counter);
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endmodule
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