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30 lines
707 B
Systemverilog
30 lines
707 B
Systemverilog
`default_nettype none
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module flip
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( input var i_clk
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, output var o_ledr
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, output var o_ledg
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, output var o_ledb
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);
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logic [31:0] counter;
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logic [2:0] leds;
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always_ff @(posedge i_clk)
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if (counter > 32'd192_000_000) counter <= '0;
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else counter <= counter + 1;
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always_comb
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if (counter < 24_000_000) {leds} = 3'b000;
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else if (counter < 48_000_000) {leds} = 3'b001;
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else if (counter < 72_000_000) {leds} = 3'b010;
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else if (counter < 96_000_000) {leds} = 3'b011;
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else if (counter < 120_000_000) {leds} = 3'b100;
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else if (counter < 144_000_000) {leds} = 3'b101;
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else if (counter < 168_000_000) {leds} = 3'b110;
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else {leds} = 3'b111;
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always_comb {o_ledr, o_ledg, o_ledb} = leds;
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endmodule
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