mirror of
https://github.com/supleed2/EIE4-FYP.git
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313 lines
12 KiB
Python
Executable file
313 lines
12 KiB
Python
Executable file
#!/usr/bin/env python3
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# Modified from original gsd_orangecrab.py from LiteX-Boards.
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#
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# Copyright (c) Greg Davill <greg.davill@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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from migen import *
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from migen.genlib.misc import WaitTimer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import LiteXModule
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from litex_boards.platforms import gsd_orangecrab
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from litex.build.generic_platform import IOStandard, Subsignal, Pins, Misc
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16
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from litedram.phy import ECP5DDRPHY
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from dacVolume import DacVolume
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from testLED import TestLed
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from testRGB import TestRgb
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from testSaw import TestSaw
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# CRG ---------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
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self.rst = Signal()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk48 = platform.request("clk48")
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rst_n = platform.request("usr_btn", loose=True)
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if rst_n is None: rst_n = 1
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk48)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# USB PLL
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if with_usb_pll:
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self.cd_usb_12 = ClockDomain()
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self.cd_usb_48 = ClockDomain()
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usb_pll = ECP5PLL()
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self.submodules += usb_pll
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self.comb += usb_pll.reset.eq(~por_done)
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usb_pll.register_clkin(clk48, 48e6)
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usb_pll.create_clkout(self.cd_usb_48, 48e6)
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usb_pll.create_clkout(self.cd_usb_12, 12e6)
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# FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
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reset_timer = WaitTimer(int(48e6))
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reset_timer = ClockDomainsRenamer("por")(reset_timer)
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self.submodules += reset_timer
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self.comb += reset_timer.wait.eq(~rst_n)
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self.comb += platform.request("rst_n").eq(~reset_timer.done)
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class _CRGSDRAM(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
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self.rst = Signal()
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self.cd_init = ClockDomain()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_i = ClockDomain()
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self.cd_dac = ClockDomain() # Custom clock domain for PCM1780 DAC
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk48 = platform.request("clk48")
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rst_n = platform.request("usr_btn", loose=True)
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if rst_n is None: rst_n = 1
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk48)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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sys2x_clk_ecsout = Signal()
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self.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 24e6)
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pll.create_clkout(self.cd_dac, 36.864e6) # Create 36.864 MHz Clock for PCM1780 (48kHz fs * 768 as in datasheet)
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self.specials += [
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Instance("ECLKBRIDGECS",
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i_CLK0 = self.cd_sys2x_i.clk,
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i_SEL = 0,
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o_ECSOUT = sys2x_clk_ecsout),
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Instance("ECLKSYNCB",
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i_ECLKI = sys2x_clk_ecsout,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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]
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# USB PLL
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if with_usb_pll:
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self.cd_usb_12 = ClockDomain()
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self.cd_usb_48 = ClockDomain()
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usb_pll = ECP5PLL()
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self.submodules += usb_pll
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self.comb += usb_pll.reset.eq(~por_done)
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usb_pll.register_clkin(clk48, 48e6)
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usb_pll.create_clkout(self.cd_usb_48, 48e6)
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usb_pll.create_clkout(self.cd_usb_12, 12e6)
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# FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
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reset_timer = WaitTimer(int(48e6))
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reset_timer = ClockDomainsRenamer("por")(reset_timer)
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self.submodules += reset_timer
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self.comb += reset_timer.wait.eq(~rst_n)
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self.comb += platform.request("rst_n").eq(~reset_timer.done)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, revision="0.2", device="25F", sys_clk_freq=48e6, toolchain="trellis",
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sdram_device = "MT41K64M16",
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with_led_chaser = True,
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**kwargs):
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platform = gsd_orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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crg_cls = _CRGSDRAM if kwargs.get("integrated_main_ram_size", 0) == 0 else _CRG
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self.crg = crg_cls(platform, sys_clk_freq, with_usb_pll=True)
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# SoCCore ----------------------------------------------------------------------------------
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# Defaults to USB ACM through ValentyUSB.
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kwargs["uart_name"] = "usb_acm"
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on OrangeCrab", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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available_sdram_modules = {
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"MT41K64M16": MT41K64M16,
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"MT41K128M16": MT41K128M16,
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"MT41K256M16": MT41K256M16,
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"MT41K512M16": MT41K512M16,
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}
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sdram_module = available_sdram_modules.get(sdram_device)
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ddram_pads = platform.request("ddram")
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self.ddrphy = ECP5DDRPHY(
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pads = ddram_pads,
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sys_clk_freq = sys_clk_freq,
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dm_remapping = {0:1, 1:0},
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cmd_delay = 0 if sys_clk_freq > 64e6 else 100)
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self.ddrphy.settings.rtt_nom = "disabled"
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if hasattr(ddram_pads, "vccio"):
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self.comb += ddram_pads.vccio.eq(0b111111)
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if hasattr(ddram_pads, "gnd"):
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self.comb += ddram_pads.gnd.eq(0)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = sdram_module(sys_clk_freq, "1:2"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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# self.leds = LedChaser(
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# pads = platform.request_all("user_led"),
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# sys_clk_freq = sys_clk_freq)
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# self.leds = TestLed(
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# platform = platform,
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# pads = platform.request_all("user_led")
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# )
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self.leds = TestRgb(
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platform = platform,
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pads = platform.request_all("user_led")
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)
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# GPIO Pins --------------------------------------------------------------------------------
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platform.add_extension([
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("dac_pcm", 0,
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Subsignal("sck", Pins("G4")), # IO_A4
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Subsignal("bck", Pins("N17")), # IO_0
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Subsignal("lrck", Pins("M18")), # IO_1
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Subsignal("data", Pins("T17")), # IO_A5
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IOStandard("LVCMOS33")
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),
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("dac_ctrl", 0,
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Subsignal("ms", Pins("N15")), # IO_MISO
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Subsignal("mc", Pins("R17")), # IO_SCK
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Subsignal("md", Pins("N16")), # IO_MOSI
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IOStandard("LVCMOS33")
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),
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("debug_uart", 0,
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Subsignal("tx", Pins("B8")), # IO_10
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Subsignal("rx", Pins("C8")), # IO_9
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IOStandard("LVCMOS33")
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)
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])
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# DAC Control / Audio Blocks ---------------------------------------------------------------
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self.audio = TestSaw(
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platform = platform,
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pads = platform.request("dac_pcm")
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)
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self.dac_vol = DacVolume(
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platform = platform,
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pads = platform.request("dac_ctrl")
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)
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# LiteScope Analyzer -----------------------------------------------------------------------
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self.add_uartbone(name="debug_uart", baudrate=921600)
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from litescope import LiteScopeAnalyzer
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analyzer_signals = [
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self.dac_vol.volume.re,
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self.dac_vol.volume.storage,
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self.dac_vol.m_sel_n,
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self.dac_vol.m_clock,
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self.dac_vol.m_data,
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self.audio.targ0.re,
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# self.audio.targ0.storage,
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self.audio.wave0.re,
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# self.audio.wave0.storage,
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self.audio.backpressure_48,
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# self.audio.sample_48,
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self.audio.audioready_48,
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self.audio.readrequest_36,
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# self.audio.sample_36,
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self.audio.fifoempty_36,
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self.audio.dac_lrck,
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self.audio.dac_bck,
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self.audio.dac_data,
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]
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from math import ceil, floor
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analyzer_depth = floor(190_000 / ((ceil(sum([s.nbits for s in analyzer_signals]) / 16)) * 16))
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self.submodules.analyzer = LiteScopeAnalyzer(
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analyzer_signals,
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depth = analyzer_depth,
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# clock_domain = "dac",
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clock_domain = "sys",
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# samplerate = 36.92e6, # Actual clock frequency of DAC clock domain
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samplerate = sys_clk_freq,
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csr_csv = "analyzer.csv",
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=gsd_orangecrab.Platform, description="LiteX SoC on OrangeCrab.")
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parser.add_target_argument("--sys-clk-freq", default=48e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--revision", default="0.2", help="Board Revision (0.1 or 0.2).")
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parser.add_target_argument("--device", default="25F", help="ECP5 device (25F, 45F or 85F).")
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parser.add_target_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
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parser.add_target_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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revision = args.revision,
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device = args.device,
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sdram_device = args.sdram_device,
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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args.csr_csv = "csr.csv"
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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