mirror of
https://github.com/supleed2/EIE4-FYP.git
synced 2024-09-19 21:36:17 +00:00
136 lines
5.4 KiB
Systemverilog
136 lines
5.4 KiB
Systemverilog
`default_nettype none
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module genWave
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( input var i_clk48 // 48MHz clock
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, input var i_rst48_n // Active low reset
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, input var i_pause // Pause sample generation (backpressure)
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, input var [ 5:0] i_osc_sel // Oscillator select, to update target freq / waveform
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, input var [27:0] i_t_freq // Target frequency for selected oscillator (24.4 fixed point)
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, input var i_tf_valid // Target frequency valid pulse (i_osc_sel must be set first)
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, input var [ 7:0] i_wav_sel // Waveform select for selected oscillator
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, input var i_ws_valid // Waveform select valid pulse (i_osc_sel must be set first)
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, output var [15:0] o_sample // Output sample data (mono)
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, output var o_pulse // Output sample valid pulse
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);
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// 48kHz Clock Generation ##########################################################################
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logic [8:0] clk_div;
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always_ff @(posedge i_clk48) // Count half 48kHz cycle
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if (!i_rst48_n) clk_div <= 0;
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else if (clk_div == 9'd499) clk_div <= 0;
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else clk_div <= clk_div + 1;
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logic clk_48k;
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always_ff @(posedge i_clk48) // Generate 48kHz clock
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if (!i_rst48_n) clk_48k <= 0;
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else if (clk_div == 9'd0) clk_48k <= ~clk_48k;
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logic clk_48k_past;
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always_ff @(posedge i_clk48) // Track rising / falling edge of 48kHz clock
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clk_48k_past <= clk_48k;
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always_comb o_pulse = clk_48k && !clk_48k_past; // Detect rising edge of 48kHz clock
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// Per Oscillator Settings Capture #################################################################
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logic [27:0] t_freq [0:63];
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always_ff @(posedge i_clk48)
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if (i_tf_valid) t_freq[i_osc_sel] <= i_t_freq; // Capture target frequency
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logic [7:0] wav_sel [0:63];
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always_ff @(posedge i_clk48)
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if (i_ws_valid) wav_sel[i_osc_sel] <= i_wav_sel; // Capture waveform select
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// Per Oscillator Phase Step Generation ############################################################
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logic [5:0] ps_clk;
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always_ff @(posedge i_clk48) // Count to 64 at 48MHz
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if (!i_rst48_n) ps_clk <= '0; // Reset
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else ps_clk <= ps_clk + 1; // Increment
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logic [27:0] int_phase_step; // Phase step calc from target frequency
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always_comb int_phase_step = (28'd699 * t_freq[ps_clk]); // 699 = (2^24 / 48000) * 2 (Approximately)
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logic [15:0] phase_step [0:63]; // Shift step right correctly (2^9) * (2^4) for fixed point
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always_ff @(posedge i_clk48) phase_step[ps_clk] <= {1'b0, int_phase_step[27:13]};
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// Per Oscillator Phase Generation #################################################################
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logic [15:0] phase [0:63];
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for (genvar i = 0; i < 64; i++) begin: l_gen_phase
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always_ff @(posedge clk_48k) // Generate new phase sample on rising edge of 48kHz clock
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if (!i_rst48_n) phase[i] <= 16'd0; // Reset saw
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else if (phase_step[i] == 16'd0) phase[i] <= phase[i] >> 1; // Divide by 2 if phase_step is 0
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else if (!i_pause) phase[i] <= phase[i] + phase_step[i]; // Add phase_step if not paused (48kHz)
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end
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// Per Oscillator Sample Generation ################################################################
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logic [15:0] saw;
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always_ff @(posedge i_clk48) if (clk_div[1:0] == 2'd0) saw <= phase[clk_div[7:2]]; // Load saw to calculate sample for
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logic [15:0] square;
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always_ff @(posedge i_clk48) square <= {~saw[15], {15{saw[15]}}}; // Square wave is MSB of saw
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logic [15:0] triangle;
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always_ff @(posedge i_clk48) triangle <= saw[15] ? {saw[14], ~saw[13:0], 1'b1} : {~saw[14], saw[13:0], 1'b0}; // Triangle wave calculation
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logic [15:0] sine;
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saw2sin m_saw2sin // Sine wave calculation
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( .i_clk(i_clk48)
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, .i_saw(saw)
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, .o_sin(sine)
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);
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logic [15:0] sample;
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always_comb // Select waveform sample based on wav_sel
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case (wav_sel[clk_div[7:2]])
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8'd0: sample = saw; // Saw wave
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8'd1: sample = square; // Square wave
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8'd2: sample = triangle; // Triangle wave
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8'd3: sample = sine; // Sine wave
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default: sample = saw; // Default to phase wave
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endcase
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logic osc_valid;
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always_comb osc_valid = (clk_div < 9'd256); // 64 oscillators * 4 stages = 256 cycles
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logic [15:0] samples [0:63]; // Store samples per oscillator
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always_ff @(posedge i_clk48) if ((clk_div[1:0] == 2'd3) && osc_valid) samples[clk_div[7:2]] <= sample;
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// Combine Samples into Single Sample ##############################################################
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logic [23:0] samples_long [0:63]; // Sum all samples to get final output sample
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always_comb samples_long[0] = {8'd0, samples[0]};
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for (genvar i = 1; i < 64; i++) begin: l_gen_sample_long
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always_comb samples_long[i] = samples_long[i-1] + {{8{samples[i][15]}}, samples[i]};
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end
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logic [6:0] waves_count [0:63];
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always_comb waves_count[0] = (phase[0] != 16'd0);
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for (genvar i = 1; i < 64; i++) begin: l_gen_waves_count
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always_comb waves_count[i] = waves_count[i-1] + (phase[i] != 16'd0); // Count non-zeroes
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end
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logic [6:0] wv_cnt_1;
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always_comb wv_cnt_1 = waves_count[63] - 1; // Subtract 1 from wave count
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logic [2:0] shift; // Calculate shift amount
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always_comb shift = wv_cnt_1[6] ? 3'd7
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: wv_cnt_1[5] ? 3'd6
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: wv_cnt_1[4] ? 3'd5
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: wv_cnt_1[3] ? 3'd4
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: wv_cnt_1[2] ? 3'd3
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: wv_cnt_1[1] ? 3'd2
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: wv_cnt_1[0] ? 3'd1
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: 3'd0;
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logic [23:0] samples_sum;
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always_comb samples_sum = samples_long[63] >> shift; // Shift output sample right to get normalised output
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always_comb o_sample = samples_sum[15:0]; // Output sample is 16 bits
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endmodule
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