mirror of
https://github.com/supleed2/EIE4-FYP.git
synced 2024-09-19 21:36:17 +00:00
Aadi Desai
06fc184cc5
Output limited to 16bit as the set bitclock rate is too low for 24bit Main work was on timing issues and inconsistent output
59 lines
2.6 KiB
Systemverilog
59 lines
2.6 KiB
Systemverilog
`default_nettype none
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module dacDriver
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( input var i_clk36 // Runs at 36.864MHz (48k * 768)
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, input var i_rst36_n // Active low reset for dac_clk
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, input var i_wait // don't retrieve new packet if high
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, input var [15:0] i_sample // 16-bit sample to output
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, output var o_rdreq // Pulse 1 cycle at 36.864MHz if i_wait low
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, output var o_lrck // Runs at 48kHz (i_clk36 / 768), changes on falling edge of o_bck
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, output var o_bck // Runs at 2.304MHz (48k * 48, i_clk36 / 16)
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, output var o_data // Changes on falling edge of o_bck
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);
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logic [8:0] div_48k;
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always_ff @(posedge i_clk36) // Count half 48kHz cycle
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if (!i_rst36_n) div_48k <= 0;
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else if (div_48k == 9'd383) div_48k <= 0;
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else div_48k <= div_48k + 1;
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logic clk_48k;
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always_ff @(posedge i_clk36) // Generate 48kHz clock
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if (!i_rst36_n) clk_48k <= 0;
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else if (div_48k == 9'd0) clk_48k <= ~clk_48k;
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logic clk_48k_mid;
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always_ff @(negedge o_bck) // Track rising / falling edge of 48kHz clock (part 1)
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clk_48k_mid <= clk_48k;
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logic clk_48k_past;
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always_ff @(posedge o_bck) // Track rising / falling edge of 48kHz clock (part 2)
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clk_48k_past <= clk_48k_mid;
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always_ff @(posedge i_clk36) // Generate 2.304MHz clock
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if (!i_rst36_n) o_bck <= 0;
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else if (div_48k[2:0] == 3'd0) o_bck <= ~o_bck;
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always_ff @(posedge i_clk36) // Pulse Read Request on rising edge of 48kHz clock if i_wait low
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if (!i_rst36_n) o_rdreq <= 0;
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else if (!i_wait && clk_48k && !clk_48k_past) o_rdreq <= 1;
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else o_rdreq <= 0;
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logic [15:0] sample;
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always_ff @(posedge i_clk36) // Capture new audio sample on Read Request
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if (!i_rst36_n) sample <= '0;
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else if (!i_wait && clk_48k && !clk_48k_past) sample <= i_sample;
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always_ff @(negedge o_bck) // Update LRCK on falling edge of BCK (As in PCM1780 Datasheet)
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if (!i_rst36_n) o_lrck <= 0;
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else o_lrck <= clk_48k;
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logic [15:0] audio_buf;
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always_ff @(negedge o_bck) // Update DATA on falling edge of BCK (As in PCM1780 Datasheet)
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if (!i_rst36_n) {o_data, audio_buf} <= {25{1'b0}}; // Reset to all 0s
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else if (clk_48k && !clk_48k_past) {o_data, audio_buf} <= {sample, 1'b0}; // Load sample (L) into shifted output
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else if (!clk_48k && clk_48k_past) {o_data, audio_buf} <= {sample, 1'b0}; // Load sample (R) into shifted output
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else {o_data, audio_buf} <= {audio_buf, 1'b0}; // Shift loaded sample into o_data
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endmodule
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