supleed2/EIE4-FYP
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3 commits

Author SHA1 Message Date
Aadi Desai 81cf1ebc5c
Replace assign with always_comb in rtl/ 
Update to better match IEEE1800-2017
 2023-05-18 12:01:56 +01:00
Aadi Desai d960053a7e
Update flip.sv to cycle across colours using 48MHz 2023-03-03 17:04:22 +00:00
Aadi Desai e1b0d5c28c
Add testing SystemVerilog and LiteX Module 2023-02-26 19:40:56 +00:00