mirror of
https://github.com/supleed2/EIE4-FYP.git
synced 2024-12-22 14:15:50 +00:00
Add pulse output to can
for frame received
This commit is contained in:
parent
391c58c7c6
commit
eb55b06779
|
@ -16,6 +16,7 @@ module can
|
||||||
, output var [ 7:0] o_data5
|
, output var [ 7:0] o_data5
|
||||||
, output var [ 7:0] o_data6
|
, output var [ 7:0] o_data6
|
||||||
, output var [ 7:0] o_data7
|
, output var [ 7:0] o_data7
|
||||||
|
, output var o_pulse
|
||||||
);
|
);
|
||||||
|
|
||||||
logic rx;
|
logic rx;
|
||||||
|
@ -111,6 +112,11 @@ always_ff @(posedge i_clk)
|
||||||
if (!i_rst_n) data <= 64'd0; // Reset
|
if (!i_rst_n) data <= 64'd0; // Reset
|
||||||
else if (div_1m == 9'd1 && msg_valid) data <= b_data; // Update data if valid, at start of bit time
|
else if (div_1m == 9'd1 && msg_valid) data <= b_data; // Update data if valid, at start of bit time
|
||||||
|
|
||||||
|
always_ff @(posedge i_clk)
|
||||||
|
if (!i_rst_n) o_pulse <= 1'b0; // Reset
|
||||||
|
else if (div_1m == 9'd1) o_pulse <= msg_valid; // Output pulse if message valid, at start of bit time
|
||||||
|
else o_pulse <= 1'b0; // Clear pulse after 1 cycle (48MHz)
|
||||||
|
|
||||||
// Output data as individual bytes
|
// Output data as individual bytes
|
||||||
always_comb o_data0 = data[63:56];
|
always_comb o_data0 = data[63:56];
|
||||||
always_comb o_data1 = data[55:48];
|
always_comb o_data1 = data[55:48];
|
||||||
|
|
Loading…
Reference in a new issue