From d784f6d2515ae1a3027c08c555f16168ec13dc43 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Sun, 28 May 2023 16:07:23 +0100 Subject: [PATCH] Add sine wave generator using cordic --- .gitignore | 1 - rtl/genSaw.sv | 5 ++++- rtl/saw2sin.sv | 29 +++++++++++++++++++++++++++++ testSaw.py | 2 ++ 4 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 rtl/saw2sin.sv diff --git a/.gitignore b/.gitignore index 79d362a..f712587 100644 --- a/.gitignore +++ b/.gitignore @@ -12,4 +12,3 @@ /dump-*.vcd /*.dfu /kernel.bin -/sintest/ diff --git a/rtl/genSaw.sv b/rtl/genSaw.sv index f4e6e14..69948ee 100644 --- a/rtl/genSaw.sv +++ b/rtl/genSaw.sv @@ -45,7 +45,10 @@ logic [15:0] triangle; always_comb triangle = saw[15] ? {~saw[14:0], 1'b1} : {saw[14:0], 1'b0}; // Triangle wave calc logic [15:0] sine; -always_comb sine = saw; // TODO: Insert sine calcuation here? +saw2sin m_saw2sin // Instantiate saw2sin module +( .i_saw(saw) +, .o_sin(sine) +); always_comb // Select output waveform case (i_wave[1:0]) diff --git a/rtl/saw2sin.sv b/rtl/saw2sin.sv new file mode 100644 index 0000000..f3aee26 --- /dev/null +++ b/rtl/saw2sin.sv @@ -0,0 +1,29 @@ +`default_nettype none + +module saw2sin +( input var [15:0] i_saw +, output var [15:0] o_sin +); + +logic invert; +always_comb invert = i_saw[15]; + +logic reverse; +always_comb reverse = i_saw[14]; + +logic [15:0] qsaw; +always_comb qsaw = reverse + ? {~i_saw[13:0], 2'b01} // Reverse + : {i_saw[13:0], 2'b00}; // Normal + +logic [15:0] qsin; +cordic cordic +( .i_qph (qsaw) +, .o_sin (qsin) +); + +always_comb o_sin = invert + ? ~{1'b1, qsin[15:1]} + 1 // Invert + : {1'b1, qsin[15:1]}; // Normal + +endmodule diff --git a/testSaw.py b/testSaw.py index 5599965..43ec89d 100644 --- a/testSaw.py +++ b/testSaw.py @@ -14,6 +14,8 @@ class TestSaw(Module, AutoCSR, ModuleDoc): Set the expected frequency sawtooth wave to be output via the headphone port. """ def __init__(self, platform, pads): + platform.add_source("rtl/cordic.sv") + platform.add_source("rtl/saw2sin.sv") platform.add_source("rtl/genSaw.sv") platform.add_source("rtl/dacDriver.sv")