From cc0ab0f2b4bbc78b1d1d623c8e5017d9fd4ab343 Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Sat, 4 Mar 2023 14:54:57 +0000
Subject: [PATCH] Add useful links on gdb and zephyr

---
 readme.md | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/readme.md b/readme.md
index f36d63b..a795c2b 100644
--- a/readme.md
+++ b/readme.md
@@ -25,6 +25,14 @@
 - [Broken Flag issue when building litex](https://github.com/enjoy-digital/litex/issues/825)
 - [On-board DAC Datasheet](https://www.ti.com/product/PCM1780)
 
+### Cool Things To Note
+
+- `python -m litex.tools.litex_read_verilog ./rtl/flipPwm.sv` allows for auto-gen of the LiteX `Class` needed to create an instance, however it does not set up the `CSRStorage`.
+- [Load Application Code To CPU](https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU)
+- [Use LiteScope To Debug A SoC](https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC)
+- [Use GDB with VexRiscv CPU](https://github.com/enjoy-digital/litex/wiki/Use-GDB-with-VexRiscv-CPU)
+- [Run Zephyr On Your SoC](https://github.com/enjoy-digital/litex/wiki/Run-Zephyr-On-Your-SoC)
+
 ### Possible reference links
 
 - [OrangeCrab FPGA Product Page](https://www.latticesemi.com/products/developmentboardsandkits/orangecrab)