supleed2/EIE4-FYP
1
0
Fork 0
mirror of https://github.com/supleed2/EIE4-FYP.git synced 2024-11-09 20:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Comment out LiteScope Analyzer, low comb remaining

Browse source
This commit is contained in:
Aadi Desai 2023-06-24 20:52:22 +01:00
parent 00c35f8476
commit bb3b3b11cc
No known key found for this signature in database
1 changed files with 39 additions and 39 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

78
make.py
View file

@ -261,45 +261,45 @@ class BaseSoC(SoCCore):
# self.proptest = TestPropagation(platform = platform) # self.proptest = TestPropagation(platform = platform)
# LiteScope Analyzer ----------------------------------------------------------------------- # LiteScope Analyzer -----------------------------------------------------------------------
self.add_uartbone(name="debug_uart", baudrate=921600) # self.add_uartbone(name="debug_uart", baudrate=921600)
from litescope import LiteScopeAnalyzer # from litescope import LiteScopeAnalyzer
analyzer_signals = [ # analyzer_signals = [
# self.proptest.i_saw, # # self.proptest.i_saw,
# self.proptest.o_sin, # # self.proptest.o_sin,
self.can.can_rx, # self.can.can_rx,
self.can.can_tx, # self.can.can_tx,
# self.dac_atten.atten.re, # # self.dac_atten.atten.re,
# self.dac_atten.atten.storage, # # self.dac_atten.atten.storage,
# self.dac_atten.m_sel_n, # # self.dac_atten.m_sel_n,
# self.dac_atten.m_clock, # # self.dac_atten.m_clock,
# self.dac_atten.m_data, # # self.dac_atten.m_data,
self.audio.osc.re, # self.audio.osc.re,
# self.audio.osc.storage, # # self.audio.osc.storage,
self.audio.tf.re, # self.audio.tf.re,
# self.audio.tf.storage, # # self.audio.tf.storage,
self.audio.wav.re, # self.audio.wav.re,
# self.audio.wav.storage, # # self.audio.wav.storage,
self.audio.backpressure_48, # self.audio.backpressure_48,
# self.audio.sample_48, # # self.audio.sample_48,
self.audio.audioready_48, # self.audio.audioready_48,
self.audio.readrequest_36, # self.audio.readrequest_36,
# self.audio.sample_36, # # self.audio.sample_36,
self.audio.fifoempty_36, # self.audio.fifoempty_36,
self.audio.dac_lrck, # self.audio.dac_lrck,
self.audio.dac_bck, # self.audio.dac_bck,
self.audio.dac_data, # self.audio.dac_data,
] # ]
from math import ceil, floor # from math import ceil, floor
analyzer_depth = floor(190_000 / ((ceil(sum([s.nbits for s in analyzer_signals]) / 16)) * 16)) # analyzer_depth = floor(190_000 / ((ceil(sum([s.nbits for s in analyzer_signals]) / 16)) * 16))
self.submodules.analyzer = LiteScopeAnalyzer( # self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, # analyzer_signals,
depth = analyzer_depth, # depth = analyzer_depth,
# clock_domain = "dac", # # clock_domain = "dac",
clock_domain = "sys", # clock_domain = "sys",
# samplerate = 36.92e6, # Actual clock frequency of DAC clock domain # # samplerate = 36.92e6, # Actual clock frequency of DAC clock domain
samplerate = sys_clk_freq, # samplerate = sys_clk_freq,
csr_csv = "analyzer.csv", # csr_csv = "analyzer.csv",
) # )
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------