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Comment out LiteScope Analyzer, low comb remaining
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parent
00c35f8476
commit
bb3b3b11cc
78
make.py
78
make.py
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@ -261,45 +261,45 @@ class BaseSoC(SoCCore):
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# self.proptest = TestPropagation(platform = platform)
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# self.proptest = TestPropagation(platform = platform)
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# LiteScope Analyzer -----------------------------------------------------------------------
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# LiteScope Analyzer -----------------------------------------------------------------------
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self.add_uartbone(name="debug_uart", baudrate=921600)
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# self.add_uartbone(name="debug_uart", baudrate=921600)
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from litescope import LiteScopeAnalyzer
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# from litescope import LiteScopeAnalyzer
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analyzer_signals = [
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# analyzer_signals = [
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# self.proptest.i_saw,
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# # self.proptest.i_saw,
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# self.proptest.o_sin,
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# # self.proptest.o_sin,
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self.can.can_rx,
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# self.can.can_rx,
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self.can.can_tx,
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# self.can.can_tx,
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# self.dac_atten.atten.re,
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# # self.dac_atten.atten.re,
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# self.dac_atten.atten.storage,
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# # self.dac_atten.atten.storage,
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# self.dac_atten.m_sel_n,
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# # self.dac_atten.m_sel_n,
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# self.dac_atten.m_clock,
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# # self.dac_atten.m_clock,
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# self.dac_atten.m_data,
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# # self.dac_atten.m_data,
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self.audio.osc.re,
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# self.audio.osc.re,
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# self.audio.osc.storage,
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# # self.audio.osc.storage,
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self.audio.tf.re,
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# self.audio.tf.re,
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# self.audio.tf.storage,
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# # self.audio.tf.storage,
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self.audio.wav.re,
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# self.audio.wav.re,
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# self.audio.wav.storage,
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# # self.audio.wav.storage,
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self.audio.backpressure_48,
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# self.audio.backpressure_48,
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# self.audio.sample_48,
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# # self.audio.sample_48,
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self.audio.audioready_48,
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# self.audio.audioready_48,
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self.audio.readrequest_36,
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# self.audio.readrequest_36,
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# self.audio.sample_36,
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# # self.audio.sample_36,
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self.audio.fifoempty_36,
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# self.audio.fifoempty_36,
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self.audio.dac_lrck,
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# self.audio.dac_lrck,
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self.audio.dac_bck,
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# self.audio.dac_bck,
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self.audio.dac_data,
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# self.audio.dac_data,
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]
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# ]
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from math import ceil, floor
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# from math import ceil, floor
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analyzer_depth = floor(190_000 / ((ceil(sum([s.nbits for s in analyzer_signals]) / 16)) * 16))
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# analyzer_depth = floor(190_000 / ((ceil(sum([s.nbits for s in analyzer_signals]) / 16)) * 16))
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self.submodules.analyzer = LiteScopeAnalyzer(
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# self.submodules.analyzer = LiteScopeAnalyzer(
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analyzer_signals,
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# analyzer_signals,
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depth = analyzer_depth,
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# depth = analyzer_depth,
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# clock_domain = "dac",
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# # clock_domain = "dac",
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clock_domain = "sys",
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# clock_domain = "sys",
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# samplerate = 36.92e6, # Actual clock frequency of DAC clock domain
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# # samplerate = 36.92e6, # Actual clock frequency of DAC clock domain
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samplerate = sys_clk_freq,
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# samplerate = sys_clk_freq,
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csr_csv = "analyzer.csv",
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# csr_csv = "analyzer.csv",
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)
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# )
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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