diff --git a/rtl/genSaw.sv b/rtl/genSaw.sv
index d0dc2c0..11da2c3 100644
--- a/rtl/genSaw.sv
+++ b/rtl/genSaw.sv
@@ -5,6 +5,7 @@ module genSaw
 , input  var        i_rst48_n
 , input  var        i_pause
 , input  var [23:0] i_targetf
+, input  var [ 7:0] i_wave
 , output var [15:0] o_sample
 , output var        o_pulse
 );
@@ -32,8 +33,26 @@ always_comb int_saw_step = (24'd699 * i_targetf); // Sawtooth step calc from inp
 logic [15:0] saw_step;
 always_comb saw_step = {1'b0, int_saw_step[23:9]}; // Shift step right correctly (2^9)
 
-always_ff @(posedge clk_48k) // Generate new sample on rising edge of 48kHz clock
-  if (!i_rst48_n)    o_sample <= '0;
-  else if (!i_pause) o_sample <= o_sample + saw_step; // Add saw_step if not paused (48kHz)
+logic [15:0] saw;
+always_ff @(posedge clk_48k) // Generate new saw sample on rising edge of 48kHz clock
+  if (!i_rst48_n)    saw <= '0;
+  else if (!i_pause) saw <= saw + saw_step; // Add saw_step if not paused (48kHz)
+
+logic [15:0] square;
+always_comb square = {16{saw[15]}};
+
+logic [15:0] triangle;
+always_comb triangle = saw[15] ? {16'hFFFF - {saw[14:0], 1'b1}} : {saw[14:0], 1'b0}; // TODO: Optimise?
+
+logic [15:0] sine;
+always_comb sine = saw; // TODO: Insert sine calcuation here?
+
+always_comb // Select output waveform
+  case (i_wave[1:0])
+    2'd0: o_sample = saw;
+    2'd1: o_sample = square;
+    2'd2: o_sample = triangle;
+    2'd3: o_sample = sine;
+  endcase
 
 endmodule
diff --git a/testSaw.py b/testSaw.py
index 2ce68df..5599965 100644
--- a/testSaw.py
+++ b/testSaw.py
@@ -59,6 +59,7 @@ class TestSaw(Module, AutoCSR, ModuleDoc):
             i_i_rst48_n = ~ResetSignal(),
             i_i_pause   = self.backpressure_48,
             i_i_targetf = self.targ0.storage,
+            i_i_wave    = self.wave0.storage,
             o_o_sample  = self.sample_48,
             o_o_pulse   = self.audioready_48,
         )