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https://github.com/supleed2/EIE4-FYP.git
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Add CAN receiver / pin definitions to make.py
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14
make.py
14
make.py
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@ -27,6 +27,7 @@ from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16
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from litedram.phy import ECP5DDRPHY
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from litedram.phy import ECP5DDRPHY
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from dacVolume import DacVolume
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from dacVolume import DacVolume
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from testCAN import CanReceiver
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from testLED import TestLed
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from testLED import TestLed
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from testRGB import TestRgb
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from testRGB import TestRgb
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from testSaw import TestSaw
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from testSaw import TestSaw
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@ -213,6 +214,11 @@ class BaseSoC(SoCCore):
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# GPIO Pins --------------------------------------------------------------------------------
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# GPIO Pins --------------------------------------------------------------------------------
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platform.add_extension([
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platform.add_extension([
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("can", 0,
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Subsignal("tx", Pins("J2")), # IO_13
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Subsignal("rx", Pins("H2")), # IO_12
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IOStandard("LVCMOS33")
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),
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("dac_pcm", 0,
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("dac_pcm", 0,
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Subsignal("sck", Pins("G4")), # IO_A4
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Subsignal("sck", Pins("G4")), # IO_A4
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Subsignal("bck", Pins("N17")), # IO_0
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Subsignal("bck", Pins("N17")), # IO_0
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@ -233,6 +239,12 @@ class BaseSoC(SoCCore):
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)
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)
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])
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])
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# CAN Receiver Block -----------------------------------------------------------------------
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self.can = CanReceiver(
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platform = platform,
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pads = platform.request("can")
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)
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# DAC Control / Audio Blocks ---------------------------------------------------------------
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# DAC Control / Audio Blocks ---------------------------------------------------------------
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self.audio = TestSaw(
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self.audio = TestSaw(
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platform = platform,
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platform = platform,
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@ -248,6 +260,8 @@ class BaseSoC(SoCCore):
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self.add_uartbone(name="debug_uart", baudrate=921600)
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self.add_uartbone(name="debug_uart", baudrate=921600)
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from litescope import LiteScopeAnalyzer
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from litescope import LiteScopeAnalyzer
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analyzer_signals = [
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analyzer_signals = [
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self.can.can_rx,
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self.can.can_tx,
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# self.dac_vol.volume.re,
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# self.dac_vol.volume.re,
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# self.dac_vol.volume.storage,
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# self.dac_vol.volume.storage,
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# self.dac_vol.m_sel_n,
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# self.dac_vol.m_sel_n,
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