supleed2/EIE4-FYP
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Add CAN receiver / pin definitions to make.py

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Aadi Desai 2023-06-04 12:40:54 +01:00
parent ac92cebbae
commit a000c35f46
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1 changed files with 14 additions and 0 deletions
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14
make.py
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@ -27,6 +27,7 @@ from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16
from litedram.phy import ECP5DDRPHY from litedram.phy import ECP5DDRPHY
from dacVolume import DacVolume from dacVolume import DacVolume
from testCAN import CanReceiver
from testLED import TestLed from testLED import TestLed
from testRGB import TestRgb from testRGB import TestRgb
from testSaw import TestSaw from testSaw import TestSaw
@ -213,6 +214,11 @@ class BaseSoC(SoCCore):
# GPIO Pins -------------------------------------------------------------------------------- # GPIO Pins --------------------------------------------------------------------------------
platform.add_extension([ platform.add_extension([
("can", 0,
Subsignal("tx", Pins("J2")), # IO_13
Subsignal("rx", Pins("H2")), # IO_12
IOStandard("LVCMOS33")
),
("dac_pcm", 0, ("dac_pcm", 0,
Subsignal("sck", Pins("G4")), # IO_A4 Subsignal("sck", Pins("G4")), # IO_A4
Subsignal("bck", Pins("N17")), # IO_0 Subsignal("bck", Pins("N17")), # IO_0
@ -233,6 +239,12 @@ class BaseSoC(SoCCore):
) )
]) ])
# CAN Receiver Block -----------------------------------------------------------------------
self.can = CanReceiver(
platform = platform,
pads = platform.request("can")
)
# DAC Control / Audio Blocks --------------------------------------------------------------- # DAC Control / Audio Blocks ---------------------------------------------------------------
self.audio = TestSaw( self.audio = TestSaw(
platform = platform, platform = platform,
@ -248,6 +260,8 @@ class BaseSoC(SoCCore):
self.add_uartbone(name="debug_uart", baudrate=921600) self.add_uartbone(name="debug_uart", baudrate=921600)
from litescope import LiteScopeAnalyzer from litescope import LiteScopeAnalyzer
analyzer_signals = [ analyzer_signals = [
self.can.can_rx,
self.can.can_tx,
# self.dac_vol.volume.re, # self.dac_vol.volume.re,
# self.dac_vol.volume.storage, # self.dac_vol.volume.storage,
# self.dac_vol.m_sel_n, # self.dac_vol.m_sel_n,