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https://github.com/supleed2/EIE4-FYP.git
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Add propegation test and results waveform
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parent
b9ea99a601
commit
964d0b0c5e
46
make.py
46
make.py
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@ -251,30 +251,36 @@ class BaseSoC(SoCCore):
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# pads = platform.request("dac_ctrl")
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# )
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# Propagation Delay Test -------------------------------------------------------------------
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from testProp import TestProp
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self.proptest = TestProp(platform = platform)
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# LiteScope Analyzer -----------------------------------------------------------------------
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self.add_uartbone(name="debug_uart", baudrate=921600)
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from litescope import LiteScopeAnalyzer
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analyzer_signals = [
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self.can.can_rx,
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self.can.can_tx,
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# self.dac_vol.volume.re,
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# self.dac_vol.volume.storage,
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# self.dac_vol.m_sel_n,
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# self.dac_vol.m_clock,
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# self.dac_vol.m_data,
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self.audio.targ0.re,
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# self.audio.targ0.storage,
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self.audio.wave0.re,
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# self.audio.wave0.storage,
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self.audio.backpressure_48,
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# self.audio.sample_48,
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self.audio.audioready_48,
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self.audio.readrequest_36,
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# self.audio.sample_36,
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self.audio.fifoempty_36,
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self.audio.dac_lrck,
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self.audio.dac_bck,
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self.audio.dac_data,
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self.proptest.i_saw,
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self.proptest.o_sin,
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# self.can.can_rx,
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# self.can.can_tx,
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# # self.dac_vol.volume.re,
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# # self.dac_vol.volume.storage,
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# # self.dac_vol.m_sel_n,
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# # self.dac_vol.m_clock,
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# # self.dac_vol.m_data,
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# self.audio.targ0.re,
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# # self.audio.targ0.storage,
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# self.audio.wave0.re,
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# # self.audio.wave0.storage,
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# self.audio.backpressure_48,
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# # self.audio.sample_48,
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# self.audio.audioready_48,
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# self.audio.readrequest_36,
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# # self.audio.sample_36,
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# self.audio.fifoempty_36,
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# self.audio.dac_lrck,
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# self.audio.dac_bck,
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# self.audio.dac_data,
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]
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from math import ceil, floor
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analyzer_depth = floor(190_000 / ((ceil(sum([s.nbits for s in analyzer_signals]) / 16)) * 16))
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34
testProp.py
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34
testProp.py
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@ -0,0 +1,34 @@
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from migen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.doc import ModuleDoc
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# Test RGB Module ----------------------------------------------------------------------------------
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class TestProp(Module, AutoCSR, ModuleDoc):
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"""
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Propagation Test Module
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Test propagation delay of the genSaw block
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"""
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def __init__(self, platform):
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platform.add_source("rtl/cordic.sv")
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platform.add_source("rtl/saw2sin.sv")
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self.targ0 = CSRStorage(size = 24, description = "Oscillator 0: Target Frequency of the Sawtooth Wave")
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self.wave0 = CSRStorage(size = 8, description = "Oscillator 0: Waveform to Output")
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self.delay = Signal(3) # Update i_saw after 2^3 = 8 cycles
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self.i_saw = Signal(16)
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self.o_sin = Signal(16)
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# # #
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self.sync += self.delay.eq(self.delay + 1)
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self.sync += If(self.delay == 0, self.i_saw.eq(self.i_saw + 1))
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self.specials += Instance("saw2sin",
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i_i_clk = ClockSignal(),
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i_i_saw = self.i_saw,
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o_o_sin = self.o_sin,
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)
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25388
testPropTiming.vcd
Normal file
25388
testPropTiming.vcd
Normal file
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