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Fix genWave output glitches

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Aadi Desai 2023-06-08 16:13:32 +01:00
parent 80f82cdc10
commit 795a9d2916
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1 changed files with 2 additions and 2 deletions
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rtl/genWave.sv
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@ -127,8 +127,8 @@ always_comb shift = wv_cnt_1[6] ? 3'd7
: wv_cnt_1[0] ? 3'd1
: 3'd0;
logic [23:0] samples_sum;
always_comb samples_sum = samples_long[63] >> shift; // Shift output sample right to get normalised output
logic [23:0] samples_sum; // Shift output sample right to get normalised output
always_ff @(posedge i_clk48) samples_sum <= samples_long[63] >> shift;
always_comb o_sample = samples_sum[15:0]; // Output sample is 16 bits